# Technical Leadership Role in Test Development Engineering

**Company**: Cisco
**Location**: Bangalore, India
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Bangalore-India/ASIC-Engineer_2028554?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_536e0e69-7cf

## Description

You will take on a technical leadership role within the Test Development Engineering team, responsible for architecting, developing, and deploying Automated Test Equipment (ATE) solutions for complex ASICs and SoCs.

Your responsibilities will include:

- Test Architecture & Development: Architect, write, and debug complex ATE test programs for wafer sort and final test

- Silicon Bring-Up: Lead first-silicon ATE bring-up, characterization, and validation of complex networking processors and multi-die packages

- DFT Collaboration: Partner with Design for Test (DFT) and ASIC design teams to define testability requirements, evaluate test coverage, and simulate test vectors

- Yield & Test Time Optimization: Drive strategic initiatives for Test Time Reduction (TTR) and yield optimization without compromising test coverage or product quality

- Manufacturing Deployment: Lead the transfer and release of robust test programs to offshore assembly and test (OSAT) partners

- Mentorship & Leadership: Serve as a domain expert and technical escalation point, mentor junior engineers, and drive continuous improvement in test methodologies and automation

You will collaborate with ASIC design / DFT teams, peer Product Development Engineers & Test Engineers, and Project Managements, Test engineering, Quality & Reliability, Supply Chain Planning.

You are a highly analytical, self-directed test engineering expert with a deep understanding of ATE hardware and software.

## Skills

### Required
- ATE test development
- Electrical Engineering
- Computer Engineering
- C/C++
- Python
- Perl
- semiconductor testing fundamentals
- DC/AC parametric testing
- digital vector execution
- mixed-signal testing
- High-Speed I/O
- SerDes
- DFT architectures
- ATPG
- Logic BIST
- Memory BIST
- Boundary Scan/JTAG

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Bangalore-India/ASIC-Engineer_2028554?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)