# Physical Design Engineer

**Company**: Cisco
**Location**: Vancouver, British Columbia
**Experience**: senior
**Job type**: full-time
**Salary**: $147,400.00 - $198,200.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Vancouver-British-Columbia-Canada/ASIC-Development-Technical-Leader_2030443?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/physical-design-engineer-522c2437-e92/

## Description

The Common Hardware Group (CHG) at Cisco creates innovative hardware platforms central to the AI era. You will be part of a global team of creative experts working on Silicon One and other hardware platforms.

Your Impact:

- Develop full-chip floorplans, incorporating architecture, foundry integration guidelines, and IP placement constraints.

- Collaborate with system and package design teams to understand requirements and integrate them into the floorplan.

- Perform hierarchical implementation flow, including partition, pin assignment, clock plan, and bump planning.

- Implement RTL-to-GDSII flow, focusing on performance, power, and die size optimization.

- Analyze existing tool flows and methodologies to identify efficiency gaps and implement improvements.

- Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.

- Utilize proficiency in low-power design methodologies using UPF.

- Define signoff methodologies with foundry and standard cell IP vendors and validate them with Post-Silicon Validation teams.

- Experience using AI tools to improve productivity.

Minimum Qualifications:

- Bachelor's degree in Electrical Engineering with 8+ years of Physical Design experience, or Master's degree with 6+ years, or PhD with 3+ years.

- Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.

- Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre/Pegasus.

Preferred Qualifications:

- Experience working on Fullchip activities, including floor-planning, power-grid planning, partitioning, and pin-assignment.

- Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.

- Experience with static timing analysis and concepts, defining timing constraints and exceptions.

- Experience with custom clock (H-Tree or Mesh) at chip level.

- Experience with Python and usage of AI tools.

Benefits:

- Medical, dental, and vision insurance.

- 401(k) plan with Cisco matching contribution.

- Paid parental leave.

- Short and long-term disability coverage.

- Basic life insurance.

- Paid time away, including holidays, vacation time, and sick time.

- Optional 10 paid days per year to volunteer.

Salary Range: $147,400.00 - $198,200.00 per year

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## Skills

### Required
- Physical Design
- RTL2GDSII flow
- EDA tools
- Electrical Engineering

### Nice to have
- Fullchip activities
- hierarchical design
- timing closure
- physical design convergence
- power integrity analysis
- Python
- AI tools

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Vancouver-British-Columbia-Canada/ASIC-Development-Technical-Leader_2030443?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)