# Senior ASIC Design Engineer

**Company**: NVIDIA
**Experience**: senior
**Job type**: full-time
**Salary**: 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---Memory-Subsystem_JR2027771?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_51ea06d9-3f2

## Description

NVIDIA is looking for a Senior ASIC Design Engineer to join the Memory Subsystem Team.

As a member of the Memory Subsystem Design team, you will collaborate with architects, design verification, formal verification, and physical design teams to deliver a world-class solution. NVIDIA SOC Interconnects, ordering controllers, and memory accelerators are among the industry's most sophisticated due to complex area, latency, power, bandwidth, and quality-of-service requirements.

In this position, you will be responsible for the micro-architecture and design, including RTL design, synthesis, and timing analysis using innovative CAD tools and the latest process technologies.

Requirements:

- BS or MS in Electrical Engineering or Computer Engineering or related degree (or equivalent experience)

- 5+ years of experience

- Experience with high-speed coherent interconnects, protocol bridges, hardware-managed coherency, and system-level caches is a plus

- Experience with multiple clock domains and asynchronous interfaces is a plus

- Knowledge of industry specifications like CHI/CXL/PCI-E is a plus

- Strong proficiency in Verilog or VHDL

- Scripting language like PERL

Benefits:

- Base salary range: 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4

- Equity and benefits

## Skills

### Required
- Electrical Engineering
- Computer Engineering
- Verilog
- VHDL
- PERL

### Nice to have
- high-speed coherent interconnects
- protocol bridges
- hardware-managed coherency
- system-level caches
- CHI/CXL/PCI-E

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---Memory-Subsystem_JR2027771?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)