# Senior SoC Subsystem and I/O Architect - LPU **Company**: NVIDIA **Work arrangement**: remote **Experience**: senior **Job type**: full-time **Category**: Engineering **Industry**: Technology **Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Remote/Senior-SoC-Subsystem-and-I-O-Architect---LPU_JR2020327?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_50eca62d-49f ## Description NVIDIA is seeking a Senior SoC Subsystem & I/O Architect to join the LPU team. The role involves establishing the high-level architecture for next-generation AI and high-performance computing products. The ideal candidate will have extensive architectural expertise across SoC subsystems and uncore IPs including PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, NoC fabrics, memory systems, coherency, boot, system initialization, protection mechanisms, reliability, availability, serviceability, power management, debug, firmware interfaces, and platform initialization. **Responsibilities:** - Define high-level SoC subsystem architecture for LPU products. - Convert LPU product requirements into architectural specifications for uncore, IO, memory, firmware-facing, boot, reset, safety, fault tolerance, diagnostic, and power regulation subsystems. - Collaborate with IP teams to develop detailed build documents for PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, NoC fabrics, memory controllers, coherency blocks, MMUs/IOMMUs, boot, reset, and associated SoC infrastructure. - Specify subsystem behavior encompassing enumeration, capability discovery, configuration flows, sequence control of memory operations, data consistency, address mapping, interrupt handling, virtualization, error handling, and firmware/software-visible controls. - Build or guide functional and architectural models from specifications, using C++, SystemC, Python, or similar languages. - Use models to validate architecture intent, subsystem behavior, configuration sequences, and IP interactions before RTL or silicon is available. - Drive tradeoffs across bandwidth, latency, power, area, timing, scalability, reliability, security, debuggability, and software usability. - Review IP specifications, subsystem architecture documents, model behavior, verification plans, and validation strategies. - Collaborate with architecture, IP, firmware, software, RTL, verification, platform, and post-silicon teams to bring architecture decisions to completion. **Requirements:** - BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience. - 8+ years of proven experience in SoC architecture, subsystem architecture, IO architecture, interconnect architecture, GPU/CPU architecture, accelerator architecture, or high-performance systems. - Strong understanding of SoC architecture and uncore subsystem development. - Extensive understanding of IO and interconnect cores including PCIe, CXL, NVLink, NVLink-C2C, UCIe, AXI, CHI, or NoC fabrics. - Experience working from product requirements to architecture requirements and IP/subsystem specifications. - Experience crafting functional models, architectural models, golden models, or C/SystemC models from architecture specifications. - Solid grasp of memory ordering, coherency, address translation, interrupts, virtualization, MMUs/IOMMUs, enumeration, configuration, and error management. - Solid knowledge of boot, reset, firmware handoff, capability discovery, security, RAS, debug, and power-management architecture. - Strong communication abilities and capability to harmonize architecture decisions across IP, firmware, software, verification, and product groups. **Benefits:** - Highly competitive salaries - Comprehensive benefits package - Equity eligibility Applications for this job will be accepted at least until June 30, 2026. ## Skills ### Required - SoC architecture - subsystem architecture - IO architecture - interconnect architecture - GPU/CPU architecture - accelerator architecture - high-performance systems - PCIe - CXL - NVLink - NVLink-C2C - UCIe - AXI - CHI - NoC fabrics - memory systems - coherency - boot - system initialization - protection mechanisms - reliability - availability - serviceability - power management - debug - firmware interfaces - platform initialization ### Nice to have - LPU - GPU - CPU - AI accelerator - chiplet - multi-die SoC architecture - deep learning workloads - numerics - memory architecture - bandwidth/latency tradeoffs - boot architecture - reset sequencing - secure boot - RAS - DFT - power sequencing - post-silicon validation --- Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Remote/Senior-SoC-Subsystem-and-I-O-Architect---LPU_JR2020327?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)