# Senior Memory Subsystem Firmware Engineer

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Memory-Subsystem-Firmware-Engineer_JR2020259?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_503dcb54-ad4

## Description

NVIDIA's SoC Memory Subsystem team is looking for a strong, senior DRAM firmware engineer to own memory firmware from architecture through production silicon.

You will lead in areas of DRAM initialization and training across DDR/LPDDR, drive interface tuning across process, voltage, and temperature corners, and set the direction for how we take new memory interfaces from pre-silicon to production.

### Responsibilities

- Own DRAM firmware across its lifecycle , architecture, implementation, silicon bring-up, and production tuning.

- Design and implement DRAM initialization and training sequences: training protocols, calibration algorithms, and their firmware implementation.

- Characterize and tune the DRAM interface across PVT (process / voltage / temperature) variation to hold margins across corners.

- Drive the memory bring-up and validation strategy; root-cause complex hardware/software interactions in the lab and in pre-silicon.

- Set firmware quality bar , code review, profiling, and coverage , and mentor early-career engineers on the team.

- Refine our Interface bring-up and validation strategy.

### Requirements

- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent experience).

- 6+ years of relevant DRAM / memory firmware development for high-speed LPDDR or system DDR memories.

- Strong command of DRAM initialization and training , protocols, calibration algorithms, and their implementation in firmware.

- Deep understanding of DRAM interfaces and how PVT (process / voltage / temperature) variation affects timing, training, and margining.

- Proficiency in C/C++, with a solid grasp of data structures, compilers, and build and version-control tooling.

- Excellent debugging skills; able to decompose hard, ambiguous failures from first principles.

### Nice to Have

- Breadth across DDR / LPDDR / HBM and multiple DRAM vendors.

- Signal-integrity intuition and comfort working with analog/mixed-signal behavior.

- Understanding of ASIC boot architecture.

You will also be eligible for equity and benefits.

## Skills

### Required
- DRAM firmware development
- DDR/LPDDR
- C/C++
- data structures
- compilers
- build and version-control tooling
- debugging

### Nice to have
- signal integrity
- analog/mixed-signal behavior
- ASIC boot architecture
- HBM
- multiple DRAM vendors

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Memory-Subsystem-Firmware-Engineer_JR2020259?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)