# SoC Engineering, Principal Engineer **Company**: Synopsys **Location**: Sunnyvale, California **Experience**: senior **Job type**: full-time **Salary**: $195000-$293000 **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/sunnyvale/soc-engineering-principal-engineer/44408/101617800624?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_4c44b459-823 ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You have spent years turning complex system requirements into working silicon, and you know that the hardest part is not writing RTL, it is making the right architectural decisions in week two that keep your team from hitting a wall in month six. You have led design teams through the full cycle, from early partitioning conversations to timing closure, and you understand that leadership at this level means knowing when to dive into the details and when to step back and let your engineers solve it. ### Responsibilities - Lead design teams of junior and senior engineers through full ASIC and FPGA development cycles, from specification to GDSII handoff - Partition and architect complex SOC designs from customer requirements, creating high-level and micro-architectures that balance performance, area, and power - Drive RTL development using SystemVerilog, ensuring designs meet quality standards through code reviews, lint checks, CDC/RDC analysis, and synthesis readiness - Collaborate directly with verification, DFT, and physical design teams to resolve integration issues, timing closure challenges, and design-for-test requirements - Implement complex industry-standard protocols including PCIe, Ethernet, and UCIe within customer-specific SOC designs - Develop and refine ASIC design flows and methodologies using Synopsys and vendor tools for simulation, synthesis, static timing analysis, and signoff - Work hands-on with customers ranging from startups to industry leaders across automotive, aerospace, defense, and high-performance computing markets ### The Impact You Will Have - Your architectural decisions will directly determine whether customer designs meet aggressive PPA targets in advanced process nodes - The teams you build and lead will deliver turnkey SOC designs that power next-generation AI, autonomous vehicles, and mission-critical aerospace systems - Your design methodologies will become reusable frameworks that accelerate future customer engagements across the Solutions group - The RTL quality standards you enforce will reduce verification cycles and prevent costly respins for multi-million-dollar tape-outs - Your ability to navigate complex customer requirements will unlock new business opportunities and long-term partnerships - The engineers you mentor will grow into technical leaders who carry forward the rigor and craft you bring to every design - Your work will help Synopsys customers ship products faster, with higher confidence, in markets where failure is not an option ### Requirements - Bachelor's degree in Electrical Engineering or Computer Engineering - 15+ years of hands-on experience designing and verifying ASIC or FPGA devices through multiple tape-outs or production releases - Proven experience leading design teams, including mentoring engineers and managing technical execution across project milestones - Deep understanding of the full ASIC design flow from micro-architecture through RTL development, synthesis, timing closure, and physical design handoff - Strong SystemVerilog RTL coding skills with demonstrated ability to design and review complex control and datapath logic - Working knowledge of industry-standard protocols such as PCIe, Ethernet, or UCIe in real production designs - Experience with ASIC development tools including simulators, lint tools, CDC/RDC checkers, synthesis tools, and static timing analysis platforms ### Benefits - Comprehensive medical and healthcare plans that work for you and your family - Time away programs including ETO and FTO - Family support including maternity and paternity leave, parenting resources, adoption and surrogacy assistance - ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back - Retirement plans that vary by region and country - Competitive salaries ## Skills ### Required - ASIC design - FPGA development - SystemVerilog - RTL development - synthesis - static timing analysis - PCIe - Ethernet - UCIe --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/sunnyvale/soc-engineering-principal-engineer/44408/101617800624?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)