# Principal High-Speed Interface Verification Engineer

**Company**: Synopsys
**Location**: Hyderabad, Telangana
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/hyderabad/principal-high-speed-interface-verification-engineer/44408/101580799408?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_4b5c155a-f4f

## Description

You will lead a verification team working on current and next-generation SerDes products, setting direction, reviewing test plans, and ensuring coverage closure across digital and mixed-signal domains.

Responsibilities:

- Lead a verification team working on current and next-generation SerDes products, setting direction, reviewing test plans, and ensuring coverage closure across digital and mixed-signal domains

- Modify and extend existing UVM and VMM SystemVerilog testbenches to co-simulate mixed-signal designs, bridging digital logic with analog models in tools like AMS Designer or Xcelium

- Analyze and verify high-speed SerDes functionality including clock data recovery, equalization, and link training across protocols like PCIe Gen5/6, 400G Ethernet, and USB3.1

- Define verification test plans with clear coverage goals, track progress against milestones, and drive closure on functional, code, and assertion coverage

- Debug simulation failures that span both analog waveforms and digital logic, working with mixed-signal engineers to isolate root cause and validate fixes

- Manage customer escalations on verification quality, silicon bugs, or testbench issues, and lead pre-sales technical discussions to support customer evaluations and design wins

Requirements:

- MTech or BTech with 15+ years of hands-on verification experience in ASIC development, with significant time spent on mixed-signal or SerDes designs

- Deep knowledge of the full ASIC development flow from architecture specification through digital design, verification, physical implementation, and hardware bring-up

- Extensive experience building and running UVM testbenches, including writing constrained random tests, developing scoreboards, and managing coverage-driven verification closure

- Practical experience with digital/analog co-simulation methodologies using tools like Cadence AMS Designer, Synopsys VCS AMS, or equivalent mixed-signal simulation environments

- Strong understanding of high-speed interface protocols such as PCIe (Gen3 or higher), Ethernet (10G/25G/50G/100G/400G), USB3.1, or similar SerDes-based standards

- Proven ability to lead technical teams, manage customer escalations, and communicate complex verification issues clearly to both engineering teams and external stakeholders

- Experience debugging at the boundary between digital logic and analog circuits, including familiarity with reading SPICE netlists, interpreting analog waveforms, and understanding signal integrity concepts is a strong plus

## Skills

### Required
- ASIC development
- mixed-signal designs
- SerDes products
- UVM testbenches
- digital/analog co-simulation
- high-speed interface protocols

### Nice to have
- debugging
- signal integrity concepts
- SPICE netlists

---

Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/hyderabad/principal-high-speed-interface-verification-engineer/44408/101580799408?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)