# Senior ASIC Design Engineer

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Salary**: 136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer--Memory-Controller_JR2029629?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/senior-asic-design-engineer-4adaadec-42a/

## Description

NVIDIA is looking for a Senior ASIC Design Engineer for our Memory Controller team!

As a Senior ASIC Engineer, you'll join a group of hard-working engineers to craft and implement innovative Memory Controllers for our Tegra SoCs! At Nvidia, you'll make a real impact in a multifaceted, technology-focused company. Your work will affect product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

### Responsibilities

- Collaborate with architects, software engineers, and circuit designers to deliver an extraordinary solution.

- Be responsible for micro-architecture and design, including RTL design, synthesis, functional verification, and timing analysis using groundbreaking CAD tools and the latest process technologies.

### Requirements

- BS, MS, or PhD in Electrical Engineering, Computer Engineer, or related degree required (or equivalent experience).

- 5+ years of relevant and proven ASIC design experience and a background in DRAM memory and/or processor design (Graphics, Microprocessors, Network Processors, or Mobile / Multimedia SOCs).

- Extensive experience in micro-architecture and RTL development.

- Relevant experience with various stages in the ASIC design flow, including functional and formal verification, emulation, synthesis & timing analysis, power estimation, and ECO.

- Strong understanding of Verilog or System Verilog.

- Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors, and circuits.

- Programming skills in C and/or PERL/PYTHON.

- Good communication and interpersonal skills.

### Preferred Qualifications

- Background with DDR, LPDDR, GDDR, or HBM memories.

- Knowledge of working with Mixed signal circuit integration and verification.

- Experience with RISCV or ARM processor architecture.

- Silicon Bring up & lab debug experience.

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4. You will also be eligible for equity and benefits.

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## Skills

### Required
- ASIC design
- RTL development
- Verilog
- System Verilog
- C
- PERL
- PYTHON
- Digital systems
- VLSI design
- Computer Architecture
- Computer Arithmetic
- CMOS transistors
- circuits

### Nice to have
- DDR
- LPDDR
- GDDR
- HBM
- Mixed signal circuit integration
- RISCV
- ARM processor architecture
- Silicon Bring up
- lab debug

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer--Memory-Controller_JR2029629?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)