# Senior Design Verification Engineer - Hardware

**Company**: NVIDIA
**Location**: Shanghai
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shanghai/Senior-Design-Verification-Engineer---Hardware_JR2020485?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_45ca446f-ad3

## Description

We are seeking a Senior Design Verification Engineer to join our team in Shanghai. You will play a crucial role in ensuring the quality and functionality of our hardware IPs.

Responsibilities:

- Participate in research to improve verification methodology and automation for producing high-quality products.

- Read design specifications and create test plans, reviewing them with architecture and design engineers.

- Build block/IP testbenches using UVM methodology.

- Develop test runs and regression flows, triage failures, and assist designers in root-causing bugs.

- Create and monitor various metrics such as passing rates and functional coverage.

- Perform SOC verification on full-chip test environments for IPs.

- Analyze functional/code coverage results and work with design engineers to improve coverage scores.

- Deploy advanced verification methodologies and infrastructure for SOC/IP.

Requirements:

- Master's degree in Electrical/Computer Engineering or equivalent experience.

- 5+ years of working experience at the master's level.

- Familiarity with advanced verification methodologies, tools, and flows.

- Experience with verification flows, including test planning, testing, coverage models, testbenches, and BFM modeling.

- Deep understanding of Verilog and High-Level Verification Language (HVL).

Preferred Qualifications:

- Strong programming skills in Python and C/C++.

- Good architectural or design experience.

- Proficiency in scripting languages such as Perl, Shell, Ruby, or Python.

## Skills

### Required
- Verilog
- HVL
- UVM methodology
- test planning
- testing
- coverage models
- testbenches
- BFM modeling

### Nice to have
- Python
- C/C++
- Perl
- Shell
- Ruby

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shanghai/Senior-Design-Verification-Engineer---Hardware_JR2020485?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)