# Senior Staff Formal Verification Applications Engineer

**Company**: Synopsys
**Location**: Sunnyvale, California
**Experience**: senior
**Job type**: full-time
**Salary**: $157000-$235000
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/sunnyvale/senior-staff-formal-verification-applications-engineer/44408/101288479376?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_4532ac1e-ace

## Description

You will work as a Senior Staff Formal Verification Applications Engineer at Synopsys, a company that delivers industry-leading silicon design, IP, simulation, and analysis solutions. Your role involves leading formal verification methodology deployment at customer sites, working hands-on with their design and verification teams to integrate VC Formal into existing flows.

**Key Responsibilities:**

- Lead formal verification methodology deployment at customer sites

- Assess customer design environments and identify high-value blocks for formal analysis

- Debug and resolve tool performance issues

- Develop and deliver technical training on VC Formal features and best practices

- Collaborate with Synopsys R&D and product engineering teams to communicate customer requirements

- Apply formal verification techniques across property checking, datapath verification, and sequential equivalence checking

- Serve as the technical bridge between customers and internal engineering

**The Impact You Will Have:**

- Enable customers to close verification gaps that simulation alone cannot reach

- Drive adoption of formal methodologies that become standard practice in customer verification flows

- Improve tool performance and usability through direct customer feedback

- Build customer confidence in formal verification by delivering measurable results

- Reduce verification cycle time for complex designs

- Influence product direction by bringing field insights back to R&D

- Strengthen customer relationships through technical credibility and responsiveness

**Requirements:**

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience

- 6+ years of hands-on experience in formal verification

- Deep expertise with formal verification tools, ideally including VC Formal or equivalent platforms

- Strong understanding of SystemVerilog Assertions (SVA) and formal testbench modeling

- Proven ability to debug tool performance issues and optimize formal runs

- Experience working directly with customers or cross-functional engineering teams

- Solid grasp of RTL design, verification methodologies, and the semiconductor development lifecycle

## Skills

### Required
- formal verification
- VC Formal
- SystemVerilog Assertions
- RTL design
- verification methodologies

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/sunnyvale/senior-staff-formal-verification-applications-engineer/44408/101288479376?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)