# R&D Engineering, Staff Engineer **Company**: Synopsys **Location**: Bengaluru **Work arrangement**: onsite **Experience**: staff **Job type**: full-time **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/bengaluru/r-and-d-engineering-staff-engineer/44408/95947919888?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_4524288b-e9a ## Description ## Overview Synopsys software engineers play a crucial role in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification, and manufacturing. ## Job Description ### Job Details - Date posted: 06/02/2026 - Category: Engineering - Hire Type: Employee - Job ID: 17520 - Remote Eligible: No ### What You'll Be Doing - Design and develop RTL using Verilog and SystemVerilog for complex SoC and ASIC components that go into production silicon - Integrate IP blocks at the SoC level, building the glue logic and subsystem architecture that makes everything actually work together - Write SDC for synthesis, ensuring your constraints reflect the real timing intent and do not create downstream surprises - Run and debug lint, CDC, and synthesis checks using tools like SpyGlass, Fusion Compiler, and Encounter, resolving issues before they become integration blockers - Collaborate with verification, physical design, and architecture teams to close functional and structural issues across the design cycle - Contribute to microarchitecture discussions and translate architectural intent into working RTL that meets performance, power, and area targets - Mentor junior engineers on RTL quality, coding standards, and front-end design best practices when the opportunity arises ### The Impact You Will Have - Your RTL integration work directly enables complex SoCs to move from architecture to physical implementation without costly respins - The synthesis constraints you write determine whether the design meets timing on the first pass or requires weeks of iteration - Your ability to debug CDC and lint issues early prevents verification and physical design teams from hitting walls later in the schedule - The glue logic and subsystem designs you build become the connective tissue that makes multi-IP integration actually function - Your technical guidance helps junior engineers avoid common pitfalls and build higher-quality RTL from the start - The blocks you own and deliver on schedule keep entire project timelines on track - Your collaboration across teams ensures that architectural intent, RTL implementation, and physical constraints stay aligned throughout the design cycle ### What You'll Need - Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related field with a minimum of 5 years of related experience, or a Master’s degree with 3 years of relevant experience - Hands-on experience in RTL design and SoC or ASIC integration, with a track record of owning blocks through synthesis - Strong proficiency in Verilog and SystemVerilog for production RTL development - Solid understanding of digital design fundamentals, microarchitecture, and SoC integration challenges - Experience running lint tools like SpyGlass or Leda, CDC analysis tools, and synthesis flows using Fusion Compiler or Encounter - Ability to write SDC and debug synthesis issues in complex, multi-clock designs - Ability to use AI tools (git hub copilot or others) - Experience with high-speed interfaces like PCIe, USB, AXI, I2C, or JTAG is a strong plus, as is familiarity with low-power design techniques and scripting in Python, Tcl, or Perl ### Who You Are - You can look at a 10,000-line RTL module and spot the structural issue that is going to cause a synthesis problem three steps downstream - You do not wait for perfect specs. You read what is available, flag the gaps, and start building while the architecture team fills in the details - When a CDC violation shows up in a report, you can quickly determine whether it is a real cross-domain hazard or a false positive from an overly conservative tool setting - You communicate clearly with people who do not speak RTL. You can explain a clock domain crossing issue to a verification engineer or a constraint tradeoff to a physical design lead without losing the technical thread - You take ownership. If a block is yours, you see it through lint, CDC, synthesis, and handoff, and you do not consider it done until the next team can actually use it - You are comfortable mentoring others, not because you have all the answers, but because you know how to help someone work through a problem without just giving them the solution ### The Team You'll Be Part Of Your recruiter will share more about the team structure and mission during the interview process. ### Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. ## Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page - ### Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. - ### Time Away In addition to company holidays, we have ETO and FTO Programs. - ### Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. - ### ESPP Purchase Synopsys common stock at ## Skills ### Required - RTL design - SoC or ASIC integration - Verilog - SystemVerilog - digital design fundamentals - microarchitecture - SoC integration challenges - lint tools - CDC analysis tools - synthesis flows - SDC - AI tools - high-speed interfaces - low-power design techniques - scripting in Python - Tcl - Perl --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/r-and-d-engineering-staff-engineer/44408/95947919888?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)