# Senior ASIC Power Management Micro Architect, Chip Design

**Company**: NVIDIA
**Location**: Yokneam, Israel
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Yokneam/Senior-ASIC-Power-Management-Micro-Architect--Chip-Design_JR2023127?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_43243754-19c

## Description

NVIDIA is the engine of modern AI and accelerated computing, and power efficiency sits at the heart of everything we build. We are looking for a Senior ASIC Design Engineer to join our Chip Design team and take ownership of Power Management IP , from micro-architecture definition all the way through to post-silicon enablement.

You will be a key player in developing and enabling new technologies that scale across NVIDIA's product lines. If you are passionate about front-end micro-architecture and design and want to see your blocks come to life in silicon, we want to hear from you!

### Responsibilities

- Owning the front-end micro-architecture and design of Power Management IP ASIC blocks, from the IP definition phase through the full design cycle and into post-silicon bring-up and enablement.

- Serving as a key player in the development and enablement of new power management technologies across NVIDIA's product lines.

- Delivering high-quality, synthesizable RTL as part of the IP Chip Design team.

- Partnering closely with architecture, verification, physical design, and validation teams to drive successful tape-out and silicon bring-up.

- Leading post-silicon debug, characterization, and enablement activities to bring your blocks from concept to working silicon.

### Requirements

- BSc or MSc in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience).

- 12+ years of hands-on RTL design experience.

- Proven experience bringing a block from the development phase all the way through to post-silicon bring-up and enablement.

- Strong background in front-end ASIC micro-architecture and design.

- Solid command of the full IP/ASIC design flow, from definition through post-silicon.

- A collaborative mindset and the drive to be a key contributor within a world-class design team.

### Nice to Have

- Hands-on experience with Power Management IP.

- A track record of contributing to new technology development and enablement.

- Deep post-silicon validation and debug expertise.

- Familiarity with low-power design techniques and methodologies.

## Skills

### Required
- RTL design
- ASIC micro-architecture
- Power Management IP
- IP/ASIC design flow
- post-silicon bring-up and enablement

### Nice to have
- low-power design techniques
- post-silicon validation and debug

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Yokneam/Senior-ASIC-Power-Management-Micro-Architect--Chip-Design_JR2023127?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)