# Signal Integrity Engineer

**Company**: OpenAI
**Location**: San Francisco
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: $225K – $445K • Offers Equity
**Category**: Engineering
**Industry**: Technology
**Wikidata**: https://www.wikidata.org/wiki/Q124605186

**Apply**: https://jobs.ashbyhq.com/openai/97507b0b-1d56-4801-ab20-4f22fe221593
**Canonical**: https://yubhub.co/jobs/job_419e4f2f-d74

## Description

## Signal Integrity Engineer

### Location

San Francisco

### Employment Type

Full time

### Department

Scaling

### Compensation

- $225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

### Benefits

- Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

- Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

- 401(k) retirement plan with employer match

- Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

- Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

- 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

- Mental health and wellness support

- Employer-paid basic life and disability coverage

- Annual learning and development stipend to fuel your professional growth

- Daily meals in our offices, and meal delivery credits as eligible

- Relocation support for eligible employees

- Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

### About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

### About the Role

We’re looking for signal integrity (SI) system design engineers who have a deep expertise in the SI area, and hold strong system level design knowledge

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

### In this role, you will:

- Lead system signal integrity (SI) design for AI supercomputer product in the data center application.

- Collaborate with chip, package, boards, rack and system engineers, design partners to drive system SI design and develop innovative interconnect and high-speed technologies

- Identify and evaluate new technologies and methodologies to improve signal and power integrity in product design, and contribute to the development of new products and technology by providing expertise in signal integrity

- Perform simulation and modeling to identify and troubleshoot signal integrity issues

- Lead system interconnect design, bring up and qualification

- As the scope of the role and team grows, understand and influence roadmaps for hardware partners for our datacenter networks, racks, and buildings.

### You might thrive in this role if you:

- Have at least 10 years of industry experience, including experience design hardware system and SerDes testing for data center applications

- Have a strong bias toward action, and won’t take no for an answer.

- Have experience and good knowledge of system design experience in the SI areas, from chip, SerDes, board, rack level

- Have experience with PCB, connector and cable design

- Have a strong intrinsic desire to learn and fill in missing skills; and an equally strong talent for sharing that information clearly and concisely with others.

- Are comfortable with ambiguity and rapidly changing conditions.

## Skills

### Required
- signal integrity
- system level design
- chip design
- package design
- board design
- rack design
- system engineering
- SerDes testing
- PCB design
- connector design
- cable design

### Nice to have
- AI native silicon
- custom design tools
- methodologies
- innovative interconnect
- high-speed technologies
