# ASIC Digital Design, Principal Engineer **Company**: Synopsys **Location**: Mississauga, Ontario **Work arrangement**: onsite **Experience**: senior **Job type**: full-time **Salary**: $146000-$219000 **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/mississauga/asic-digital-design-principal-engineer-18731/44408/100945625264?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_41214601-261 ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Our team develops high-speed silicon IP solutions with a primary focus on PCIe PHY technology. These IPs enable customers to integrate advanced connectivity into SoCs faster while meeting demanding performance, power, area, and reliability targets. We are looking for a senior verification leader to drive the strategy, execution, and quality of next-generation PCIe PHY IP verification. You are an experienced ASIC Verification Engineer with a strong track record of delivering high-quality mixed-signal IP products, especially high-speed SerDes-based PHYs. You bring deep expertise in digital verification methodologies and have strong domain knowledge in PCIe PHY architectures, link behavior, LTSSM, power management, equalization, and interoperability requirements. **Responsibilities** - Define and drive the verification strategy and functional quality for next-generation PCIe PHY IPs. - Develop comprehensive verification plans for complex mixed-signal digital designs with primary emphasis on PCIe PHY functionality and protocol compliance. - Architect, develop, and execute advanced testbench environments for block-level and subsystem-level verification. - Verify key PCIe PHY features such as LTSSM behavior, PIPE interface interactions, link initialization and training, power management, equalization flows, error handling, and compliance-related scenarios. - Work closely with design, analog, firmware, architecture, and validation teams to ensure robust coverage of cross-functional use cases. - Use advanced verification methodologies, including constrained-random, assertion-based verification, coverage-driven verification, and debug automation, to achieve high-quality results. - Analyze failures, root-cause complex issues, and drive resolution across design and verification domains. - Mentor and guide other engineers, promote verification best practices, and help build a culture of technical excellence and continuous improvement. - Communicate effectively with internal stakeholders and customers to align on technical goals, verification quality, and deliverables. **Requirements** - Extensive experience in mixed-signal ASIC/IP verification. - Strong expertise in PCIe and PCIe PHY verification. - Solid understanding of high-speed SerDes/PHY architecture and digital control verification in mixed-signal environments. - Hands-on experience with modern verification methodologies such as SystemVerilog, UVM, assertions, and coverage-driven verification. - Experience developing verification plans, building reusable verification environments, and closing coverage for complex IP products. - Strong debugging and problem-solving skills, with the ability to work independently and drive issues to closure. - Excellent communication and collaboration skills for working across global, cross-functional teams. - Proven ability to mentor engineers and lead technical verification activities. **Benefits** - Comprehensive medical and healthcare plans that work for you and your family. - In addition to company holidays, we have ETO and FTO Programs. - Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. - Purchase Synopsys common stock at a 15% discount, with a 24-month look-back. - Save for your future with our retirement plans that vary by region and country. - Competitive salaries. ## Skills ### Required - PCIe PHY verification - mixed-signal ASIC/IP verification - SystemVerilog - UVM - assertions - coverage-driven verification --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/mississauga/asic-digital-design-principal-engineer-18731/44408/100945625264?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)