# Senior/Staff ASIC Design Verification Engineer

**Company**: Synopsys
**Location**: Ho Chi Minh City
**Work arrangement**: onsite
**Experience**: senior/staff
**Job type**: employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/ho-chi-minh-city/senior-staff-asic-design-verification-engineer/44408/92568976592
**Canonical**: https://yubhub.co/jobs/job_40a899dc-af8

## Description

Our organisation is seeking a skilled Senior/Staff ASIC Design Verification Engineer to join our team in Ho Chi Minh City, Vietnam. As a key member of our engineering team, you will be responsible for designing and developing cutting-edge semiconductor solutions. Your expertise in ASIC RTL design flow, RTL and GLS verification, and high-speed interface protocols will be essential in advancing our technology and enabling innovations in various industries.

Key Responsibilities:

* Collaborate with digital design teams to develop high-speed mixed-signal PHY IPs.
* Participate in RTL and Gate-Level Simulation (GLS) verification for mixed-signal designs.
* Define, develop, and execute functional verification plans and test strategies.
* Conduct RTL and SDF-annotated gate-level simulations using UVM-based methodologies.
* Generate VCD files and perform power analysis/reporting using PrimeTime PX.

Requirements:

* Minimum of 2 years of experience in ASIC RTL design flow.
* Proficiency in RTL and GLS verification, with strong debugging capabilities.
* Excellent teamwork and communication skills, with professional proficiency in English.
* Strong knowledge of high-speed interface protocols (e.g., DDR, HBM, or PCIe PHYs) is a distinct advantage.

Benefits:

* Comprehensive medical and healthcare plans that work for you and your family.
* In addition to company holidays, we have ETO and FTO Programs.
* Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
* Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
* Save for your future with our retirement plans that vary by region and country.
* Competitive salaries.

## Skills

### Required
- ASIC RTL design flow
- RTL and GLS verification
- High-speed interface protocols
- UVM-based methodologies
- PrimeTime PX

### Nice to have
- High-speed interface protocols