# Principal RTL Design Engineer, Interconnect IP (PCIe digital design and architecture) **Company**: Synopsys **Location**: Bengaluru, Karnataka **Work arrangement**: onsite **Experience**: senior **Job type**: full-time **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/bengaluru/principal-rtl-design-engineer-interconnect-ip-pcie-digital-design-and-architecture/44408/93996748480?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_3e97a707-ad1 ## Description You will join Synopsys, the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. As a Principal RTL Design Engineer, Interconnect IP (PCIe digital design and architecture), you will own the PCIe digital architecture and drive RTL design execution across block, subsystem, and IP integration levels. ### Responsibilities - Own the PCIe digital architecture and drive RTL design execution across block, subsystem, and IP integration levels, staying directly involved in design decisions and reviews - Define micro-architecture, design specifications, and implementation strategies for high-performance, power-efficient, and scalable PCIe IP - Lead end-to-end digital design activities from architecture definition through RTL development, debug, design convergence, and post-silicon support - Serve as the technical authority for PCIe design, resolving complex issues and making critical design trade-offs that affect current and next-generation IP - Mentor ASIC digital design engineers through design reviews, technical feedback, and hands-on problem solving - Collaborate with verification, physical design, formal, emulation, firmware, and system teams to ensure seamless IP integration and silicon success - Drive design quality through rigorous reviews, coding standards, and maintainability practices that raise the bar across the team ### The Impact You Will Have - Deliver industry-leading PCIe digital IP that powers silicon for customers building next-generation products across commercial, enterprise, and automotive markets - Strengthen the technical foundation and execution quality of PCIe designs used by leading semiconductor companies - Influence the technical strategy and roadmap for Synopsys PCIe and interconnect IP, shaping architecture decisions that affect multiple product generations - Raise the technical capability of the team through mentorship, design leadership, and knowledge sharing that builds long-term strength - Improve design predictability, quality, and execution efficiency through strong architectural leadership and disciplined engineering practices - Drive Synopsys' position as a leader in high-speed interface IP by delivering robust, scalable, and silicon-proven solutions - Enable faster time-to-market for customers by delivering PCIe IP that integrates cleanly and performs reliably in complex SoC environments ### Requirements - Bachelor's degree in Electrical Engineering with 12+ years of ASIC digital design experience, or Master's degree with 10+ years - Demonstrated experience as a technical lead or principal engineer driving complex ASIC digital design projects - Deep expertise in PCIe digital design and architecture, with direct ownership of RTL design and micro-architecture definition - Strong understanding of ASIC design fundamentals including clocking, resets, low-power techniques, and design for test - Proven ability to drive designs from concept through silicon, including post-silicon debug and support - Experience with CXL, DDR, AMBA, UCIe, or related high-speed interconnect protocols is highly desirable - Familiarity with AI-driven design tools, scripting languages like Perl, TCL, or Python for design automation is a plus ## Skills ### Required - PCIe digital design - RTL design - ASIC design - micro-architecture definition - design specifications - implementation strategies ### Nice to have - CXL - DDR - AMBA - UCIe - AI-driven design tools - Perl - TCL - Python --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/principal-rtl-design-engineer-interconnect-ip-pcie-digital-design-and-architecture/44408/93996748480?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)