# Senior ASIC Design Verification Engineer - Slingshot

**Company**: Hewlett Packard Enterprise
**Location**: Chippewa Falls, Wisconsin
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: USD 147,000 - 279,000 in Colorado // 140,000 - 321,000 in Minnesota & Wisconsin
**Category**: Engineering
**Industry**: Technology

**Apply**: https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Chippewa-Falls-Wisconsin-United-States-of-America/Senior-ASIC-Design-Verification-Engineer---Slingshot_1218135-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_3c874e02-d63

## Description

We are seeking a Senior ASIC Design Verification Engineer to work on the HPE Slingshot interconnect, a high-performance interconnect used in HPC and AI systems.

As a Senior Design Verification Engineer, you will work alongside experienced architects, logic designers, and verification engineers on the switch and NIC ASICs for a future generation of Slingshot.

Responsibilities:

- Follow and help define the team's design verification methodology

- Develop SystemVerilog and UVM testbench components

- Plan and implement block and integration level scoreboards and checkers

- Write and analyze functional coverage

- Triage regression failures and identify logic bugs

- Apply scripting, automation, and AI-assisted tools to improve verification efficiency

- Provide guidance and mentoring to less experienced staff members

Requirements:

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent

- 10+ years of experience in VLSI design, verification, or implementation

- Expert level knowledge of SystemVerilog and OVM or UVM methodologies

- Expert level analytical and problem-solving skills

Preferred Skills:

- Experience verifying high-speed networking, switching, or NIC ASICs

- Experience with agentic AI coding tools and workflows applied to verification

- Experience with Python, Perl, Tcl, or another scripting language in Linux development environments

We offer a comprehensive suite of benefits that support physical, financial, and emotional wellbeing, as well as opportunities for personal and professional development.

The expected salary/wage range for this position is:

- United States of America: Annual Salary USD 147,000 - 279,000 in Colorado // 140,000 - 321,000 in Minnesota & Wisconsin

## Skills

### Required
- SystemVerilog
- OVM or UVM methodologies
- analytical and problem-solving skills

### Nice to have
- Python
- Perl
- Tcl
- agentic AI coding tools and workflows

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Source: [Apply at hpe.wd5.myworkdayjobs.com](https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Chippewa-Falls-Wisconsin-United-States-of-America/Senior-ASIC-Design-Verification-Engineer---Slingshot_1218135-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)