# Director of Digital Design Engineering, Memory Interface IP **Company**: Synopsys **Location**: Hyderabad, Telangana **Work arrangement**: onsite **Experience**: senior **Job type**: full-time **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/hyderabad/director-of-digital-design-engineering-memory-interface-ip/44408/100624924096?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_3989ad77-cc8 ## Description You will lead a team building memory interface IP that powers the next wave of AI and high-performance compute. ## Job Description You have spent years deep in the world of high-speed memory interfaces, where timing closure is measured in picoseconds and a single protocol violation can sink a tape-out. You know HBM, DDR, and LPDDR not as acronyms but as living systems with tradeoffs you have navigated across multiple generations. ### What You'll Be Doing - Lead a team of ASIC digital design and verification engineers working on HBM, DDR, and LPDDR memory interface IP - Own the technical direction and execution of RTL design and verification at both block and chip integration levels - Drive design reviews, architecture decisions, and quality checkpoints across the full development cycle from spec to silicon - Collaborate with cross-functional teams including analog design, DFT, physical design, and product management to align on specifications, schedules, and deliverables - Build and refine design and verification methodologies, incorporating AI-driven tools and automation to improve efficiency and quality - Manage project timelines, resource allocation, and risk mitigation to deliver on schedule and within scope - Mentor and develop engineers, providing technical guidance and career growth opportunities across the team ### The Impact You Will Have - Deliver memory interface IP that enables the next generation of AI accelerators, data center processors, and high-performance SoCs - Raise the bar for design quality and verification coverage across one of the most performance-critical IP domains in the industry - Shape the technical roadmap for high-speed memory controllers that will be integrated into products shipping at scale - Build a high-performing team culture where engineers grow, ship complex designs, and solve hard problems together - Accelerate time to market by driving adoption of advanced methodologies, automation, and AI-assisted design flows - Strengthen Synopsys' leadership position in memory interface IP by delivering differentiated, production-proven solutions - Influence product strategy and customer engagements through deep technical insight and execution credibility ### What You'll Need - 15 - 20+ years of experience in ASIC digital design and verification, with significant hands-on work in memory interface IP such as HBM, DDR, or LPDDR - Proven track record leading engineering teams through full product development cycles from architecture to silicon bring-up - Deep expertise in RTL design, verification methodologies, and design closure for high-speed digital interfaces - Strong understanding of memory protocols, PHY/controller architecture, signal integrity, and timing closure challenges - Experience managing cross-functional collaboration with analog, physical design, and product teams - Demonstrated ability to communicate technical risks, tradeoffs, and project status to executive leadership and stakeholders - Experience with AI-driven design tools or a strong interest in integrating AI into design and verification flows is a plus ## Skills ### Required - ASIC digital design - verification - memory interface IP - HBM - DDR - LPDDR - RTL design - design closure - AI-driven design tools --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/hyderabad/director-of-digital-design-engineering-memory-interface-ip/44408/100624924096?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)