# ASIC Implementation Technical Lead

**Company**: Cisco
**Location**: San Jose, California
**Experience**: senior
**Job type**: full-time
**Salary**: $186,900.00 to $267,700.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-DFT-Engineering-Technical-Leader_2028145?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_387d68ef-e20

## Description

The Silicon One team at Cisco is looking for an ASIC Implementation Technical Lead with a primary focus on Design-for-Test.

You will work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.

Key responsibilities include:

- Crafting groundbreaking next-generation networking chips

- Leading the DFT and quality process through the entire Implementation flow and post-silicon validation phases

- Working with ATE engineers on pattern translation and validation

Requirements:

- Bachelor’s degree in Electrical or Computer engineering and 8+ years of experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of experience, or PhD in Electrical Engineering or Computer Engineering + 3 years of experience

- Prior experience with ATPG and EDA tools like TestMax or Tetramax or Tessent or similar tool sets

- Prior experience working with Gate level simulation, including timing-based simulations with SDF, debugging with VCS and other simulators

- Prior post-silicon validation and debug experience

- Prior experience with scan insertion

Preferred qualifications:

- Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification

- Prior experience with EDA tools like Tessent

- Prior experience with Jtag protocols (p1500, p1687)

- Prior experience with SSN

- Scripting skills: Tcl, Python/Perl

- Prior experience with test static timing analysis constraints development and timing closure

Benefits:

- Medical, dental and vision insurance

- 401(k) plan with a Cisco matching contribution

- Paid parental leave

- Short and long-term disability coverage

- Basic life insurance

- Paid time away (vacation, holidays, sick time)

- Opportunities for professional growth and development

## Skills

### Required
- ATPG
- EDA tools
- TestMax
- Tetramax
- Tessent
- Gate level simulation
- SDF
- VCS
- post-silicon validation
- scan insertion

### Nice to have
- Verilog
- DFT logic
- IP integration
- functional verification
- Jtag protocols
- SSN
- Tcl
- Python/Perl
- test static timing analysis

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-DFT-Engineering-Technical-Leader_2028145?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)