# SOC Engineering, Sr Staff Engineer **Company**: Synopsys **Location**: Bengaluru, Karnataka **Work arrangement**: onsite **Experience**: senior **Job type**: full-time **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/bengaluru/soc-engineering-sr-staff-engineer/44408/96200212512?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_376ddcb3-7d2 ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. **Job Description** We are seeking a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs. **Responsibilities** - Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs. - Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets. - Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities. - Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence. - Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions. - Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency. - Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed. **Impact** - Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide. - Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations. - Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys. - Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise. - Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction. - Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes. **Requirements** - Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field. - 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm). - Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification. - Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime. - Strong scripting and automation skills using Python, PERL, TCL, or similar languages. - Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs. - Exposure to high-frequency design and low-power design methodologies. **Team** You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry. **Rewards and Benefits** We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. ## Skills ### Required - RTL2GDSII flows - synthesis - place & route - clock tree synthesis (CTS) - timing optimization - static timing analysis (STA) - physical verification - EMIR analysis - timing closure - block-level and full-chip floor-planning - Python - PERL - TCL - high-frequency design - low-power design methodologies --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/soc-engineering-sr-staff-engineer/44408/96200212512?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)