# Director of Digital Verification, High speed ethernet IP development

**Company**: Synopsys
**Location**: Bengaluru, Karnataka
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/bengaluru/director-of-digital-verification-high-speed-ethernet-ip-development/44408/102470445600?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/director-of-digital-verification-high-speed-3497326c-547/

## Description

You will lead verification for high-speed Ethernet IP that ships into products across the industry, and the team you build will set the standard for how we verify Interface IP.

### Job Description

You have spent years building verification environments that actually catch the bugs that matter, the ones that would have delayed tape-out or broken customer trust. You know that verification is not just about coverage metrics, it is about understanding the design deeply enough to know where it will break before it does.

You will:

- Lead a team of ASIC verification engineers designing, implementing, and optimizing verification environments for high-speed Ethernet and other Interface IP protocols including PCIe, CXL, DDR, and AMBA

- Own the technical direction and execution of verification strategy at both block level and full chip integration, making the calls on what gets verified when and how deeply

- Build and refine verification methodologies, incorporating AI-driven automation tools to improve efficiency, reduce manual effort, and close coverage faster

- Create and track detailed test plans that map to real design risk, not just spec checkboxes, and drive them through execution and closure

- Manage project timelines, resource allocation, and risk mitigation across multiple concurrent IP development efforts to deliver on schedule and within scope

- Collaborate directly with RTL design and architecture teams to identify, root-cause, and resolve bugs before they reach integration

- Mentor and develop verification engineers in UVM best practices, SystemVerilog techniques, and how to think like an attacker when writing tests

### Requirements

- 15+ years of hands-on experience in ASIC digital verification, with deep expertise in at least two Interface IP protocols such as PCIe, CXL, DDR, Ethernet, or AMBA (CHI, AXI, AHB, APB)

- Proven track record leading verification teams through full IP or chip development cycles from architecture through tape-out

- Strong technical proficiency in SystemVerilog, SVA, and UVM methodologies, with the ability to review code and architecture at a detailed level

- Solid understanding of the full digital ASIC and IP development flow, including RTL design, synthesis, timing, and how verification fits into the broader workflow

- Experience with industry-standard simulation tools such as VCS, ModelSim, or equivalent, and familiarity with formal verification and emulation is a plus

- Strong analytical and problem-solving skills with a demonstrated ability to tackle complex, ambiguous verification challenges and drive them to resolution

- Excellent communication skills with the ability to influence cross-functional teams, present technical strategies to leadership, and collaborate effectively with design, architecture, and product teams

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## Skills

### Required
- ASIC digital verification
- Interface IP protocols
- SystemVerilog
- SVA
- UVM methodologies
- RTL design
- synthesis
- timing

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/director-of-digital-verification-high-speed-ethernet-ip-development/44408/102470445600?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)