# Senior ASIC Verification Engineer

**Company**: Hewlett Packard Enterprise
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: Annual Salary USD 158,500 - 321,000
**Category**: Engineering
**Industry**: Technology

**Apply**: https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Sunnyvale-California-United-States-of-America/Senior-ASIC-Verification-Engineer_1210391-2?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_3484c929-e9a

## Description

We are seeking a Senior ASIC Verification Engineer to join our team. As a Senior ASIC Verification Engineer, you will provide technical expertise and lead project teams of Electronic and VLSI engineers and internal and outsourced development partners responsible for all stages of VLSI design and development for complex products, solutions, and platforms, including design, validation, and testing.

Responsibilities:

- Provide technical expertise and lead project teams of Electronic and VLSI engineers and internal and outsourced development partners

- Review and evaluate designs and project activities for compliance with VLSI technology and development guidelines and standards

- Provide VLSI-specific and technical expertise along with the overall architecture design and platform leadership to cross-organization projects, programs, and activities

- Lead project teams of VLSI engineers and internal and outsourced development partners to develop reliable, cost-effective, and high-quality solutions for VLSI prototypes and products

- Mentor less experienced staff members to set an example of VLSI design and development innovation and excellence

- Participate in the selection process for future technical leaders

- Drive VLSI innovation and integration of new technologies into projects and activities in the design organization

- Develop detailed test plans to verify modules

- Write functional models for modules using System Verilog/C/C++ for architectural validation

- Build module-level test benches using System Verilog/UVM

- Write tests according to test plans to thoroughly verify modules

- Work closely with logic designers to resolve bugs and with SW engineers to assist in driver code development

- Use state-of-the-art tools for formal verification, code coverage analysis, gate sims, and more

- Participate in full chip/sub-system and emulation testing

- Participate in ASIC validation in the lab

- Mentor interns and new college graduates

Education and Experience Required:

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent

- 6-10 years of experience in VLSI design, verification, or implementation

Knowledge and Skills:

- Expert-level proficiency in electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture

- Expert-level analytical and problem-solving skills

- Expert-level knowledge of designing VLSI components, integrated circuitry, architectures, and algorithms into VLSI solutions

- Experience in constrained-random verification with methodologies such as UVM

- Knowledge of Perl/Python/C/C++

- Excellent written and verbal communication skills

## Skills

### Required
- VLSI design
- verification
- System Verilog
- UVM
- Perl
- Python
- C
- C++
- Electrical Engineering
- Computer Engineering

### Nice to have
- Computer Architecture
- networking protocols
- machine learning

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