# ASIC Physical Design, Manager **Company**: Synopsys **Location**: Bengaluru, Karnataka **Work arrangement**: onsite **Experience**: senior **Job type**: full-time **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/bengaluru/asic-physical-design-manager/44408/102771667680?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_33f08b3f-0c9 ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You have spent years in the trenches of ASIC physical design, and you know that tape out success is not about heroics at the end, it is about the flow you set up, the checks you automate, and the decisions you make when the schedule says one thing and the timing report says another. You have managed teams through multiple silicon cycles and learned that the best managers do not just delegate tasks, they clear blockers, teach judgment, and know when to dive into a floorplan yourself because it is faster than explaining it three times. ### Responsibilities - Lead a team of physical design engineers responsible for building and maintaining the complete PD flow and methodology for the Testchip team, from RTL handoff through GDSII delivery - Drive end-to-end execution of multiple testchip projects, managing timing closure, power optimization, and physical verification using tools like ICC2, Fusion Compiler, PrimeTime, and Calibre - Set up and continuously improve design automation flows across physical design stages, including scripting for repeatability, quality checks, and faster closure cycles - Collaborate with front-end design, silicon validation, and software teams to align on design intent, verify handoffs, and troubleshoot issues that span multiple domains - Manage project schedules, resource allocation, and risk mitigation to hit tape out dates while maintaining quality and design robustness - Serve as the technical point of contact for foundry interactions, translating foundry requirements into actionable design constraints and managing DRC/LVS closure - Mentor engineers on timing analysis, floorplanning, place and route strategies, and verification best practices, building depth and judgment across the team ### The Impact You Will Have - Deliver high-quality, high-performance testchips that validate Synopsys embedded memory IP and enable faster customer adoption of next-generation products - Accelerate time-to-market for Synopsys customers by ensuring robust, repeatable tape outs that meet performance, power, and area targets - Strengthen Synopsys technical reputation through successful project delivery, post-silicon support, and proactive customer engagement - Drive measurable improvements in physical design methodology, reducing closure time, improving PPA, and increasing automation across the testchip flow - Grow engineering talent within the organization by mentoring engineers into technical leads and building a culture of ownership and continuous learning - Influence future product direction by feeding silicon learnings back into IP development and strategic planning discussions - Build stronger foundry partnerships through technical collaboration, early engagement on process nodes, and clear communication during bring-up and debug ### Requirements - 8 to 14 years of hands-on experience in ASIC physical design, with at least 2 years leading teams or managing projects - Proven track record of multiple successful tape outs, ideally across different process nodes or design complexities - Deep expertise in physical design implementation, timing closure, power optimization, and physical verification using industry-standard EDA tools like Fusion Compiler, ICC2, PrimeTime, Tempus, Calibre, or equivalent - Strong understanding of the complete chip design flow from RTL to GDSII, including handoff points, verification stages, and common failure modes - Experience setting up design automation flows, scripting for physical design tasks, and improving methodology for timing closure and verification - Experience in front-end design or RTL methodologies is a significant plus and will help you bridge design intent with physical implementation - Demonstrated ability to manage people, projects, and cross-functional collaboration in a technical environment with competing priorities ### Benefits - Comprehensive medical and healthcare plans that work for you and your family - Time away programs including ETO and FTO - Maternity and paternity leave, parenting resources, adoption and surrogacy assistance - ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back - Retirement plans that vary by region and country - Competitive salaries ## Skills ### Required - ASIC physical design - RTL-to-GDSII flow - timing closure - power optimization - physical verification - EDA tools ### Nice to have - front-end design - RTL methodologies --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/asic-physical-design-manager/44408/102771667680?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)