# Senior Logic Design Engineer

**Company**: NVIDIA
**Location**: Santa Clara, CA, US, CA
**Experience**: senior
**Job type**: full-time
**Salary**: 168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Silicon-Architect---Cache-Coherent-Interconnects_JR2029189?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_33c6cc41-32c

## Description

We are seeking a Senior Logic Design Engineer to join our CPU Cache Coherent Interconnects Design Team.

As a member of this team, you will be responsible for the silicon architecture and construction of our CPU processors, focusing on tasks such as dielet partitioning, packaging and die-stacking exploration, floorplanning and die-to-die interface planning.

**Responsibilities**

- Own the silicon architecture and construction plan for next-generation CPU processors.

- Explore 2D multi-chip module, 2.5D interposer and 3D hybrid-bonded dielet constructions, including the placement of IO and compute (CPU cores, caches and NOC) across dielets.

- Develop early floorplans, and plan die-to-die and off-chip IO, including UCIe, DRAM and PCIe.

- Work with architecture, logic design, physical design and packaging teams to achieve area, performance, power and thermal goals.

**Requirements**

- Master's Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.

- 8+ years of experience in processor or other related high-performance semiconductor designs.

- Deep understanding of digital design, CPU system architecture and ASIC floor-planning, including wire densities on-die and across 3D connected dies.

- Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

**Preferred Qualifications**

- A strong background in cache coherency or high-speed interconnects and industry-standard coherency/IO/memory protocols.

- Knowledge of advanced packaging (TSMC InFO and CoWoS, Intel EMIB), through-silicon via configurations and backside power delivery, along with Dielet, Interposer, Substrate connectivity.

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5. You will also be eligible for equity and benefits.

## Skills

### Required
- Electrical Engineering
- Computer Engineering
- Computer Science
- digital design
- CPU system architecture
- ASIC floor-planning

### Nice to have
- cache coherency
- high-speed interconnects
- industry-standard coherency/IO/memory protocols
- advanced packaging
- through-silicon via configurations
- backside power delivery

---

Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Silicon-Architect---Cache-Coherent-Interconnects_JR2029189?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)