# ASIC Digital Design Manager **Company**: Synopsys **Location**: Bengaluru, Karnataka **Work arrangement**: onsite **Experience**: senior **Job type**: full-time **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/bengaluru/asic-digital-design-manager/44408/101601440336?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_32a86ccd-142 ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You have spent a decade building IP that ships, not just passes verification. You know that the best microarchitecture is the one that survives contact with timing closure, power constraints, and the realities of a 5nm process node. You have been the person in the room who catches the CDC issue before it becomes a silicon respin, and you have learned that the hardest part of leading a design team is not writing the cleanest RTL, it is teaching five engineers to think three steps ahead without micromanaging their every line of code. At Synopsys, you will lead a team building Ethernet MAC and PCS controllers that power networking silicon across the industry. The work is technically hard, the team is real, and what you build will matter. ### Responsibilities - Lead a team of digital design engineers developing Ethernet MAC and PCS IP from microarchitecture specification through customer release - Drive architectural and microarchitectural decisions for next-generation Ethernet controllers, translating customer requirements into robust, scalable RTL implementations in SystemVerilog - Oversee design reviews, timing closure strategy, CDC/RDC sign-off, and synthesis quality across multiple concurrent IP development projects - Manage resource allocation, project execution, and cross-functional collaboration with verification, physical design, and product teams to meet schedule and quality commitments - Conduct technical interviews, assess candidate capabilities in RTL design and microarchitecture, and build a high-performing team through hiring and onboarding - Mentor engineers on complex implementation challenges including high-speed interface design, multi-voltage domain architectures, and UPF-based low-power methodologies - Own performance reviews, career development planning, and succession planning for your team while fostering a culture of technical excellence and continuous learning ### The Impact You Will Have - Deliver Ethernet IP that powers networking products across the semiconductor industry, enabling high-speed connectivity in data centers, automotive, and AI systems - Build and scale a digital design team capable of executing complex IP development projects with quality, predictability, and technical rigor - Strengthen Synopsys IP portfolio by driving architectural innovation and design reuse across Ethernet MAC, PCS, and related high-speed interface technologies - Reduce time-to-market for customers by ensuring IP releases meet timing, power, and area targets without late-stage surprises or silicon respins - Grow the next generation of RTL design talent through mentorship, technical coaching, and hands-on leadership in real product development - Influence cross-functional execution by providing clear technical direction, risk assessment, and tradeoff analysis that keeps projects on track - Shape the technical culture of the Ethernet IP group by setting standards for design quality, code reviews, and engineering discipline ### Requirements - 10+ years of hands-on ASIC digital design experience with deep expertise in RTL development, microarchitecture, and IP design - 3+ years in a technical leadership or engineering management role, with demonstrated ability to lead, mentor, and grow design teams - Expert-level proficiency in SystemVerilog and Verilog for synthesis, with a strong track record of delivering production-quality RTL - Deep knowledge of high-speed interfaces and protocols such as Ethernet, PCIe, DDR, or AMBA AXI/AHB/APB - Strong understanding of Static Timing Analysis, synthesis, timing closure, and the ability to make microarchitectural tradeoffs that meet timing and power goals - Hands-on experience with CDC and RDC verification flows, linting, and static sign-off methodologies - Experience with low-power design techniques, UPF-based power intent definition, and multi-voltage domain architectures is a strong plus - Familiarity with advanced process nodes (7nm, 5nm, or below) or hardware/software co-verification using emulation platforms like Palladium or Zebu is a plus ### Benefits - Comprehensive medical and healthcare plans that work for you and your family - In addition to company holidays, we have ETO and FTO Programs - Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more - Purchase Synopsys common stock at a 15% discount, with a 24-month look-back - Save for your future with our retirement plans that vary by region and country - Competitive salaries ## Skills ### Required - ASIC digital design - RTL development - microarchitecture - SystemVerilog - Verilog - Static Timing Analysis - synthesis - timing closure - CDC/RDC verification ### Nice to have - low-power design techniques - UPF-based power intent definition - multi-voltage domain architectures - advanced process nodes - hardware/software co-verification --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/asic-digital-design-manager/44408/101601440336?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)