# USB Applications Principal Engineer / Manager

**Company**: Synopsys
**Location**: Yongin-si, Gyeonggi-do
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/yongin-si/usb-applications-principal-engineer-manager/44408/95924563824?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_32096fcc-148

## Description

You will be a USB Applications Principal Engineer / Manager at Synopsys, the leader in engineering solutions from silicon to systems. Your role involves providing technical support to customers integrating DesignWare USB Mixed Signal PHY IP, troubleshooting issues across synthesis, static timing analysis, and guiding customers through USB protocol implementation.

Responsibilities:

- Provide technical support to customers integrating DesignWare USB Mixed Signal PHY IP, from initial integration through silicon bring-up and debug

- Troubleshoot customer issues across synthesis, static timing analysis, design-for-test, and clock domain crossing

- Guide customers through USB 2.0, USB 3.x, and Type-C protocol implementation and design tradeoffs

- Collaborate with Synopsys R&D and product teams to escalate complex issues and feed customer requirements back into the roadmap

- Deliver technical presentations and integration best practices to customer engineering teams during design reviews

- Travel occasionally to customer sites across Korea and the region to support critical milestones

The Impact You Will Have:

- Enable customer success on high-stakes tapeouts by resolving integration issues that would otherwise delay schedules

- Reduce time-to-silicon for customers by providing clear, actionable guidance during critical design phases

- Build deep technical relationships with leading semiconductor companies in Korea as their trusted advisor

- Shape future IP releases by channeling real customer pain points back to the product team

- Expand Synopsys footprint in customer accounts through technical depth and responsiveness

- Help customers achieve first-pass silicon success, directly impacting their product launches and market reputation

Requirements:

- Bachelor's or Master's in Electrical Engineering or Computer Engineering with 10~20+ years of ASIC design or verification experience

- Strong working knowledge of synthesis, static timing analysis, design-for-test, and clock domain crossing

- Ability to work independently and drive issues to resolution in customer-driven, ambiguous situations

- Excellent communication skills in Korean and English, able to explain complex concepts clearly

- Experience with USB 2.0, USB 3.x protocols, or Type-C is a strong plus

- Willingness to travel occasionally within Korea and the region

## Skills

### Required
- ASIC design
- verification
- synthesis
- static timing analysis
- design-for-test
- clock domain crossing
- USB 2.0
- USB 3.x
- Type-C

### Nice to have
- USB protocols

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/yongin-si/usb-applications-principal-engineer-manager/44408/95924563824?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)