# Test Timing Engineer

**Company**: Cisco
**Location**: Armenia
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Armenia/Test-Timing-Engineer-Technical-Leader_2005394?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_31566238-b94

## Description

Join the dynamic Test Timing Engineering team at Cisco, a group of experts dedicated to ensuring robust and accurate timing constraints for advanced chip designs.

As a Test Timing Engineer, you will play a pivotal role in developing and validating timing constraints that ensure the accuracy and reliability of advanced chip designs.

Responsibilities:

- Own the creation and validation of timing constraints at block, sub-chip, and full-chip levels in various test modes.

- Perform quality checks, including identifying duplicated constraints and verifying unconstrained endpoints, to drive robust timing analysis.

- Develop and enhance methodologies, guidelines, and checklists to streamline static timing analysis (STA) workflows.

- Collaborate with cross-functional teams to resolve timing and design flow issues, accelerating project execution.

- Implement and maintain SDC flows and validation processes to ensure compliance and accuracy across all design stages.

Minimum qualifications:

- Bachelor’s degree in electrical or computer engineering (or equivalent field) with 8+ years of relevant work experience or Master’s degree in electrical or computer engineering (or equivalent) with 6+ years of relevant experience.

- Demonstrated experience developing block/full-chip SDC in test modes (scan shift, scan capture, ATPG capture).

- Proficiency in Static Timing Analysis (STA) and hands-on experience with tools such as PrimeTime.

- Programming proficiency in at least two scripting languages (e.g., Perl, TCL, Python, Makefile).

- Proven track record in SDC validation, timing exception handling, and STA flow development.

Preferred qualifications:

- Master’s degree in electrical or computer engineering (or equivalent) with 6+ years of relevant experience.

- Experience debugging and analyzing timing constraints for DFT modes (scan shift/capture, BIST)

- Prior hands-on experience with SDC debugging and STA tools (Synopsys GCA/TCM/PrimeTime)

- Experience with synthesis tools, especially Synopsys Fusion Compiler, and Tessent DFT insertion

- Strong communication skills and proven ability to work collaboratively within cross-functional teams

## Skills

### Required
- Static Timing Analysis
- STA
- SDC
- Perl
- TCL
- Python
- Makefile
- PrimeTime

### Nice to have
- Synopsys GCA/TCM/PrimeTime
- Synopsys Fusion Compiler
- Tessent DFT insertion

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Armenia/Test-Timing-Engineer-Technical-Leader_2005394?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)