# Memory IP Applications Engineering, Sr Staff Engineer

**Company**: Synopsys
**Location**: Raanana, Central District
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/raanana/memory-ip-applications-engineering-sr-staff-engineer/44408/101270640400?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_30762d13-187

## Description

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

As a Memory IP Applications Engineering, Sr Staff Engineer, you will provide technical guidance and hands-on support to customers integrating Synopsys Memory Sub System IPs into their ASIC SoC/systems. Your responsibilities will include:

- Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.

- Collaborating with customers to resolve technical issues related to RTL simulation, synthesis, floorplanning, timing closure, and silicon/system bring-up.

- Supporting silicon bring-up and characterization in system environments, ensuring successful deployment of Synopsys IP in customer products.

- Documenting best practices, developing application notes, and delivering training to enable customer success with Synopsys solutions.

- Participating in cross-functional teams to relay customer feedback, contribute to product improvements, and stay current with the latest interface protocols and industry standards.

The ideal candidate will have:

- Master's degree with 10+ years of industry experience or equivalent.

- At least 10+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles.

- Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure.

- Hands-on expertise in integration and validation of High Speed IPs for Memory sub system.

- Proficient in RTL and gate-level simulation debugging, with familiarity in front-end tools like Design Compiler, Fusion Compiler, and PrimeTime.

- Experience with silicon bring-up and system-level characterization in lab environments.

- Domain knowledge of memory subsystem, DDR & LPDDR protocols implementation flows.

You will join a dynamic, multi-site, highly skilled team of Applications Engineers and IP integration specialists, partnering closely with customers across the globe to provide technical expertise and integration support for industry-leading Interface IP.

## Skills

### Required
- ASIC design
- IP integration
- RTL simulation
- synthesis
- floorplanning
- timing closure
- silicon bring-up
- characterization
- DDR/LPDDR protocols

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/raanana/memory-ip-applications-engineering-sr-staff-engineer/44408/101270640400?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)