# ASIC Digital Verification, Sr Staff Engineer

**Company**: Synopsys
**Location**: Eindhoven, North Brabant
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/eindhoven/asic-digital-verification-sr-staff-engineer/44408/97475891632?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_2e45010c-22c

## Description

You will join the Security IP group at Synopsys in Eindhoven, a dedicated team advancing embedded security technologies that enable customers to build chips with cutting-edge cryptographic solutions.

As an ASIC Digital Verification, Sr Staff Engineer, you will be responsible for designing and executing verification strategies for complex security IP subsystems with digital components, including cryptographic cores, random number generators, interface modules, and memories.

Your key responsibilities will include:

- Designing and executing verification strategies for complex security IP subsystems

- Building and maintaining UVM testbenches, assertion-based verification environments, and formal verification flows for IP subsystems

- Developing test plans, test specifications, and coverage models that map to product requirements

- Automating regression environments using scripting to ensure continuous verification across design iterations

- Running verification tests in both simulator environments and on FPGA platforms

- Debugging failures at the RTL and testbench level, working directly with design engineers and architects to root-cause and resolve defects

Your expertise will help the Eindhoven team stay ahead of evolving security threats and verification methodologies. You will work on security IP protecting devices across automotive, mobile, networking, and IoT applications with an experienced Eindhoven team.

The ideal candidate will have:

- A Bachelor's or Master's degree in Electrical Engineering or Computer Science with 6+ years of hands-on verification experience

- Proven track record verifying digital hardware IP components through multiple tape-outs or product releases

- Deep expertise in SystemVerilog, UVM, assertion-based verification, coverage-driven methodology, and formal verification techniques

- Strong understanding of IC design flows, RTL design principles, and the handoff between verification and implementation

- Experience automating verification flows and building regression environments using scripting languages like Python, Perl, or TCL

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs, including competitive salaries, comprehensive medical and healthcare plans, time away, family support, ESPP, retirement plans, and more.

## Skills

### Required
- SystemVerilog
- UVM
- assertion-based verification
- formal verification
- Python
- Perl
- TCL

### Nice to have
- security protocols
- cryptographic algorithms
- embedded security

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/eindhoven/asic-digital-verification-sr-staff-engineer/44408/97475891632?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)