# Principal (STA/ Sign-Off) Engineer-17042 (Austin/ Sunnyvale)

**Company**: Synopsys
**Location**: Sunnyvale, California
**Experience**: senior
**Job type**: full-time
**Salary**: $191000-$286000
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/sunnyvale/principal-sta-sign-off-engineer-17042-austin-sunnyvale/44408/96623912992?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_2cf9a969-13b

## Description

As a member of the IP Digital Design Methodology team, you will work with global teams to define best-in-class ASIC design standards and flows and assist IP development teams.

You will be involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

You are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with STA and EM/IR flows.

With over 12+ years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development.

You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.

Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams.

Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results.

You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.

### Responsibilities

- Develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries.

- Work with leading-edge designs and teams to drive the industry-best PPA for IP designs.

- Evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO’s.

- Develop and maintain best-in-class digital design methodologies, including documentation, scripts, and training materials.

- Work as a liaison between Synopsys tool and IP design teams.

- Continuously improve and refine design processes to enhance efficiency and performance.

### Requirements

- BS or MS in EE with 12+ years of hands-on experience developing CAD flows for high-speed digital IP cores and/or SOCs.

- Direct hands-on experience with enabling advanced node STA/ Timing signoff flows at SoC level.

- Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.

- Familiarity with EMIR & Thermal sign-off flows is a plus.

- Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.

- Good analysis, debugging, and problem-solving skills.

- Solid written and verbal communication skills and the ability to create clear and concise documentation and provide training.

- Familiarity with other Synopsys tools such as StarRC and ICV is a plus.

- Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR are a plus.

## Skills

### Required
- Static Timing Analysis (STA)
- Power Analysis
- EM/IR
- ASIC design
- Synopsys tools

### Nice to have
- EMIR & Thermal sign-off flows
- StarRC
- ICV
- HDMI
- MIPI
- PCIe
- SATA
- Ethernet
- USB
- DP
- DDR

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/sunnyvale/principal-sta-sign-off-engineer-17042-austin-sunnyvale/44408/96623912992?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)