# DFT Engineer

**Company**: NVIDIA
**Location**: Bengaluru
**Experience**: mid
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/DFT-Engineer_JR2019966?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_2bf9cb9a-8b3

## Description

As a DFT Engineer at NVIDIA, you will work on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification, and post-silicon validation on some of the industry's most complex semiconductor chips.

Responsibilities:

- Verify state-of-the-art Memory BIST logic and other DFT circuits like JTAG, IO BIST, and ATPG.

- Validate test features with robust and scalable test plan development at unit-level and SOC/Full Chip level using verification methodologies like UVM and NVIDIA Internal tools.

- Simulate Pre-Silicon Simulation and Debug of Test functionality using standard Industry tools and sign-off on Test coverage for various products using standard coverage metrics.

- Work on automation, flow development and improvement, coverage metrics, test execution, bug identification/fix, and Memory-test productization.

- Collaborate with design teams to understand architecture and with QA engineers to deliver good test coverage and improve software quality.

Requirements:

- BTech/BE/BS or MTech/ME/MS in EE/ECE or equivalent experience.

- Solid analytical and problem-solving skills.

- Good understanding and exposure to logic design, architecture, and verification.

- Strong coding skills in industry-standard scripting languages.

- Exposure to DFT circuits and methodology.

- 1+ year of experience in industry-standard verification flows like constrained random testing, UVM, coverage metrics, profiling tools, etc. will be a plus.

- Outstanding written and oral communication skills with a curiosity to learn.

## Skills

### Required
- DFT architecture
- verification
- post-silicon validation
- Memory BIST logic
- JTAG
- IO BIST
- ATPG
- UVM
- Python
- Perl

### Nice to have
- constrained random testing
- coverage metrics
- profiling tools

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/DFT-Engineer_JR2019966?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)