# Senior DFT Methodology Engineer

**Company**: NVIDIA
**Experience**: senior
**Job type**: full-time
**Salary**: 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-DFT-Methodology-Engineer_JR2026899?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_27264c14-e77

## Description

We are seeking a Senior DFT Methodology Engineer to architect and develop test methodologies for our next-generation silicon, ensuring it is testable, debuggable, and secure from the outset.

As a Senior DFT Methodology Engineer, you will work with cross-functional teams to implement state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, memory dump, and DFX security methodology.

You will partner closely with timing, physical design, software, bring-up, and production teams to balance cost and quality, and help architect, develop, and deploy DFT methodologies for our next-generation products, including RTL design, verification, pattern generation, and collaboration with teams like timing, physical design, software, bring-up, and production.

Additionally, you will mentor junior engineers on test designs and trade-offs, including cost and quality.

The ideal candidate will have:

- A BS/MS in Electrical or Computer Engineering (or equivalent experience) with 10+ years of hands-on experience in SoC architecture, RTL design, and verification.

- Strong analytical skills, with experience using vendor tools to verify and validate test patterns and logic on highly complex, multi-million-gate designs.

- Good exposure to cross-functional areas, including RTL & clocks design, STA, place-n-route, and power.

- Experience in silicon debug and bring-up on the ATE, with an understanding of pattern formats, failure processing, and test program development.

- Exceptional written and oral interpersonal skills.

Preferred qualifications include knowledge of DFT security and hardware system security, strong programming and scripting skills in Perl, Python, or Tcl, a proven track record of deploying advanced DFT methodologies, experience mentoring engineers, and strong problem-solving skills.

In return, you will receive a competitive salary (ranging from 168,000 USD to 310,500 USD, depending on level and location), equity, and comprehensive benefits.

## Skills

### Required
- DFT
- SoC architecture
- RTL design
- verification
- test access mechanisms
- I1149.1
- I1500
- I1687
- 1838
- memory BIST
- memory dump
- DFX security methodology

### Nice to have
- DFT security
- hardware system security
- Perl
- Python
- Tcl
- scripting
- problem-solving

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-DFT-Methodology-Engineer_JR2026899?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)