# ASIC Verification/Design Engineering Intern

**Company**: Hewlett Packard Enterprise
**Location**: Roseville, California
**Work arrangement**: hybrid
**Experience**: entry
**Job type**: internship
**Salary**: Hourly Salary USD 35.00 - 41.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Roseville-California-United-States-of-America/ASIC-Verification-Design-Engineering-Intern_1214211?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_266ebc91-5b4

## Description

This intern will be working with the HPE Aruba ASIC development team on next-generation products, contributing to the development activities of current or future ASICs.

The ASIC team develops state-of-the-art, world-class Networking Chips for the marketplace and customers. The intern will work with and learn from senior members of the ASIC/VLSI team.

Responsibilities may include:

- RTL/Physical Design

- Pre-Silicon verification

- Post-silicon verification

- Formal Verification

- Script and/or Tool development

- Schedule breakdowns

- Document generation

The intern will be working on a summer project that will be used for/in the development activities of current or future ASICs.

**Education & Experience:**

- Currently enrolled in a 4-year University/College pursuing a degree in Computer Engineering, Computer Science, Electrical Engineering or equivalent.

- At least 3rd Year of engineering courses completed (December 2027 or May 2028 degree completion).

**Knowledge & Skills:**

- Experience with scripting languages (Python, PERL, TCL or equivalent)

- Experience with hardware design

- Experience with software programming languages (C, C++)

- Experience with Verilog

- Strong interest in high-tech and a passion for learning

- Excellent communication and interpersonal skills

- Strong problem-solving and analytical skills

- Time management skills and working with strict deadlines

- A collaborative, solution-focused mindset and overall sense of urgency

- Experience with AI tools

**Benefits:**

- Comprehensive suite of benefits that supports physical, financial, and emotional wellbeing

- Investment in career development

- Unconditional inclusion and celebration of individual uniqueness

**Salary:** Hourly Salary USD 35.00 - 41.00 in California

## Skills

### Required
- Python
- PERL
- TCL
- C
- C++
- Verilog
- hardware design
- software programming
- AI tools

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Source: [Apply at hpe.wd5.myworkdayjobs.com](https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Roseville-California-United-States-of-America/ASIC-Verification-Design-Engineering-Intern_1214211?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)