# ASIC Physical Design Intern

**Company**: Synopsys
**Location**: Yerevan
**Job type**: internship
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/yerevan/asic-physical-design-intern/44408/102166693184?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_2589a951-f3d

## Description

Our internship programs offer real-world projects, hands-on experience, and opportunities to collaborate with teams globally.

As an ASIC Physical Design Intern at Synopsys, you will work on real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide.

**The Team You’ll Be A Part Of:** Join a dynamic team focused on advancing ASIC physical design. We push technological boundaries and ensure high standards of quality and performance, fostering an inclusive and supportive work environment.

**What You’ll Be Doing:**

- Work on the backend ASIC design flow, from netlist to GDSII, as well as the physical verification of standard cell libraries.

- Analyze and debug physical verification results.

- Collaborate with cross-functional teams to support design and verification activities.

**What You’ll Need:**

- Currently studying in the 3rd or final year of Electronics Engineering, Telecommunications, Automation & Control, Computer Science, or a related field.

- Good knowledge of UNIX/Linux operating systems.

- Basic understanding of Shell and TCL scripting for process automation and day-to-day tasks.

- Basic knowledge of VLSI technology; familiarity with standard cell libraries and PDKs would be a plus.

- Good English communication skills.

- Strong self-learning, research, and presentation skills.

- Accountable, patient, and motivated, with a strong work ethic.

- Ability to learn quickly and work effectively both independently and as part of a team.

**The Impact You Will Have:**

- Contribute to the successful validation of standard cell libraries.

- Support high-quality ASIC physical design and verification activities.

- Explore and apply AI-enabled tools to support engineering workflows and continuous improvement.

## Skills

### Required
- UNIX/Linux
- Shell scripting
- TCL scripting
- VLSI technology
- English communication

### Nice to have
- standard cell libraries
- PDKs

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/yerevan/asic-physical-design-intern/44408/102166693184?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)