# Signal and Power Integrity Engineer

**Company**: NVIDIA
**Location**: Shenzhen
**Work arrangement**: onsite
**Experience**: mid
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shenzhen/Signal-and-Power-Integrity-Engineer_JR2017700?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_22d6f3c3-be6

## Description

We are now looking for a Signal & Power Integrity Engineer to join our team. As a Signal & Power Integrity Engineer at NVIDIA, you will drive board/system level signal and power integrity requirements, lead board/system SI/PI design activities, and work closely with various teams to design and ensure system SI/PI performance meets expectation.

Responsibilities: Drive board/system level signal and power integrity requirements Lead board/system SI/PI design activities, including PCB stackup/material selection, design guide implementation, layout review, and post-layout analysis Work closely with Architecture, ASIC, Mixed Signal, Package, and PCB Design teams to design and ensure system SI/PI performance meets expectation before Gerber out, also work closely with Design Validation teams to support SI/PI failure analysis Develop novel algorithms & new methodologies to improve SI/PI modeling efforts Work with Application Engineering teams to support customers w/ SI/PI questions VNA & TDR measurements to support model correlation efforts and improve confidence in design stage

Requirements: MS/BS in EE or equivalent experience Minimum 1+ years of experience as a SI/PI engineer Deep understanding of electromagnetic, specifically electromagnetic waves including transmission line theory and via properties Proficient with HFSS, Sigrity, Hspice, and/or other simulation tools Experienced with Cadence Allegro PCB designer and Constraints Manager Understanding of high volume manufacturing variations and impact to channel signal integrity Exposure to lab measurements including VNA & TDR experience Passionate about SI/PI work Good written & verbal interpersonal skills in English

Ideally, you will have familiarity with NRZ/PAM-4 signaling schemes, exposure to interface timing budgets and system modeling, familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes, PDN analyses including model generation and time domain simulation, and experience w/ Matlab, Python, and C as well as exposure to package design.

## Skills

### Required
- HFSS
- Sigrity
- Hspice
- Cadence Allegro PCB designer
- Constraints Manager
- Matlab
- Python
- C

### Nice to have
- NRZ/PAM-4 signaling schemes
- interface timing budgets and system modeling
- high-speed I/O design concepts
- clock generation
- transmitter & receiver design
- equalization schemes
- PDN analyses
- package design

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shenzhen/Signal-and-Power-Integrity-Engineer_JR2017700?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)