# Digital Design Lead

**Company**: Cisco
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Pune-India/ASIC-Engineering-Digital-Designer--Leader---digital-design--FSM--CPU-sub-systems--complex-SOCs--FPGA-validation---8-12-Years---Pune-_2013154?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_220cbbc8-787

## Description

Cisco's Client Optics Group (COG) designs and delivers high-speed optical transceivers and platforms that power Cisco's core data center networking solutions. As a Digital Design Lead, you will provide technical leadership in the development of digital logic for silicon photonics, ensuring high-performance outcomes for optical interconnects. You will manage the full ASIC lifecycle, from architectural conception to tapeout and post-silicon production support, while overseeing the integration of digital logic with analog and mixed-signal blocks.

Responsibilities include:

- Contributing individually during all design activities from Pre-Silicon RTL to GDS2 signoff and post-silicon activities

- Designing complex digital blocks and CPU subsystems

- Propagating top-level specifications to block-level specifications for high-speed datapath and low-speed control planes

- Reviewing verification coverage and signing off on coverage metrics

- Supporting all backend activities such as synthesis, timing closure, DFT, and low-power design

Minimum qualifications:

- Bachelor's or master's degree in electrical engineering, electronics engineering, or a related field

- 8-12 years of industry experience with hands-on experience in digital design

- Familiarity with protocols such as SPI, I2C, APB, AXI, or similar interfaces and high-speed SerDes, Ethernet, D2D PHY IP, and protocols

- Strong knowledge of ASIC/SoC design flow, including RTL development using SystemVerilog, simulation, lint, CDC/RDC, synthesis, formal/equivalence checking, DFT, and implementation handoff

## Skills

### Required
- ASIC/SoC design flow
- digital design
- high-speed optical interconnects
- SystemVerilog
- SerDes
- Ethernet

### Nice to have
- master's degree in electrical engineering

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Pune-India/ASIC-Engineering-Digital-Designer--Leader---digital-design--FSM--CPU-sub-systems--complex-SOCs--FPGA-validation---8-12-Years---Pune-_2013154?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)