# Senior Verification Manager, SERDES PHY **Company**: Synopsys **Location**: Mississauga, Ontario **Work arrangement**: onsite **Experience**: senior **Job type**: full-time **Salary**: $166,000-$248,000 **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/mississauga/senior-verification-manager-serdes-phy/44408/96193430288?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_21db4a3c-e52 ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. **Job Description** As a Senior Verification Manager, you will lead and grow a distributed team of verification engineers and senior technical leads working on SERDES PHY mixed-signal verification across UVM simulation, co-simulation, emulation, and lab validation. You will debug priority regressions, customer escalations, and silicon correlation issues directly, working in SystemVerilog, UVM, co-sim environments, and firmware bring-up flows. **Responsibilities** - Lead and grow a distributed team of verification engineers and senior technical leads working on SERDES PHY mixed-signal verification across UVM simulation, co-simulation, emulation, and lab validation - Debug priority regressions, customer escalations, and silicon correlation issues directly, working in SystemVerilog, UVM, co-sim environments, and firmware bring-up flows - Own verification sign-off quality and release readiness for SERDES PHY IP, including testplan review, coverage analysis, checker effectiveness, and release evidence documentation - Define and evolve UVM and mixed-signal co-simulation methodology, regression standards, reuse strategy, and automation frameworks using Shell, Perl, Python, and C++ - Partner daily with analog design, digital design, firmware, and applications teams to resolve technical blockers, align on test strategy, and close coverage gaps - Represent verification in program reviews, customer technical engagements, and cross-functional release planning meetings - Drive automation and AI-assisted regression triage where it measurably improves throughput, debug time, or coverage closure **The Impact You Will Have** - Ensure SERDES PHY IP releases meet sign-off quality for deployment in high-performance SoCs shipping to customers across automotive, data center, and AI markets - Reduce time to root cause on mixed-signal bugs by building a team that knows how to read waveforms, correlate models to silicon, and close issues without escalation loops - Establish verification methodology and reuse standards that scale across PCIe, Ethernet, and future high-speed serial IP families - Grow senior verification engineers into technical leads who can own testplans, drive coverage closure, and mentor others through complex debug - Improve regression efficiency and triage speed through targeted automation, better VIP integration, and smarter use of co-simulation and emulation platforms - Strengthen customer confidence in Synopsys SERDES IP by delivering clean releases, fast escalation response, and credible technical partnership during bring-up - Shape the technical direction of mixed-signal verification at Synopsys by contributing to tool selection, flow improvements, and cross-team best practices **What You'll Need** - 10+ years of hands-on ASIC mixed-signal verification experience with recent work in the last 3 to 5 years on debug, environment development, or sign-off - 3+ years leading verification engineers or equivalent team lead scope, including hiring, performance management, and technical mentorship - Deep experience with PCIe and/or Ethernet SERDES, high-speed serial links, DSP blocks, and clock/data recovery circuits - Strong command of SystemVerilog, UVM, VIP integration, and coverage-driven verification methodology - Proven ability in mixed-signal verification flows including co-simulation, analog/digital modeling, and lab or silicon correlation - Scripting proficiency in Shell, Perl, Python, or C++ with the ability to review and contribute to automation infrastructure - Credible technical judgment under schedule pressure, you know when to push for more coverage and when to ship with documented risk. Experience with TX/RX PMA, common-mode PLLs, firmware bring-up, or rate and power state flows is a plus. Distributed team leadership with hands-on technical engagement is a strong differentiator. **Who You Are** - You can step into a regression triage, pull up a waveform in Verdi or DVE, and guide an engineer to the root cause without doing the work for them - You know the difference between a testplan that looks complete and one that actually covers the corner cases that break in the lab, and you push back when sign-off evidence is thin - You are comfortable switching context between a hiring conversation, a firmware debug session, a customer call, and a coverage review, all in the same afternoon - You build teams that stay technical, you hire people who want to understand the PHY, not just run regressions, and you create space for them to grow into senior leads - You do not need perfect information to make a call, you work with what you have, align with design and firmware, and move forward without creating downstream chaos - You care about automation and tools, but only when they solve a real problem, you will write a Python script to fix a triage bottleneck and you will kill a dashboard nobody uses **The Team You'll Be Part Of** Your recruiter will share more about the team structure and mission during the interview process. **Rewards and Benefits** We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. ## Skills ### Required - SystemVerilog - UVM - VIP integration - coverage-driven verification methodology - co-simulation - analog/digital modeling - lab or silicon correlation - Shell - Perl - Python - C++ --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/mississauga/senior-verification-manager-serdes-phy/44408/96193430288?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)