# ASIC Design and STA Engineer

**Company**: NVIDIA
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Design-and-STA-Engineer_JR2021789-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_1e5e7e9f-2be

## Description

NVIDIA is seeking an ASIC Design and STA Engineer to join their Networking Silicon engineering team. The successful candidate will work on designing large-scale, innovative chips for high-speed communication devices, focusing on high-throughput and low-latency solutions for AI platforms.

Responsibilities:

- Lead full chip and/or chiplet-level STA convergence from early stages to signoff.

- Participate in top-level floor planning and clock planning.

- Collaborate with CAD teams to optimize signoff flows and methodologies.

- Integrate digital partitions and analog IPs' timing, providing feedback to PD/RTL teams and driving convergence.

- Work closely with logic design and DFT engineers to define and implement constraints for various work modes, optimizing for runtime and efficiency.

Requirements:

- B.Sc./M.Sc. in Electrical Engineering/Computer Engineering.

- 3+ years of experience in physical design and STA.

- Proven experience in RTL2GDS and STA design and convergence.

- Familiarity with physical design EDA tools such as Synopsys, Cadence, etc.

- Hands-on STA experience from early stages to signoff using Synopsys Primetime, with deep knowledge of timing concepts.

- Strong teamwork and collaboration skills.

## Skills

### Required
- STA
- Physical Design
- RTL2GDS
- Synopsys Primetime
- Cadence
- Synopsys

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Design-and-STA-Engineer_JR2021789-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)