# Senior Mask Layout Design Engineer

**Company**: NVIDIA
**Location**: Taipei
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Taiwan-Taipei/Senior-Mask-Layout-Design-Engineer_JR2019959?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_1da39534-63e

## Description

We are looking for a Senior Mask Layout Design Engineer to join our team responsible for handling high-speed mixed-signal circuit designs.

You will perform physical layout for mixed-signal functions like PLL's, high-speed memory I/O circuits, SerDes, general I/O's, and ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools.

Responsibilities include:

- Customizing designs for integration in VLSI products with ASIC and mixed-signal engineers

- Floor planning, custom layout, and verifying against design rules and schematics

Requirements:

- BSEE with a minimum of 5 years of relevant mask design/layout experience or equivalent experience

- Proven understanding of analog circuit layout concepts in submicron CMOS technologies

- Expertise with Cadence custom circuit design tools, particularly Virtuoso

- Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre

- Ability to communicate in spoken and written English

- Effective teamwork and interpersonal skills

- Proficiency in scripting languages like Perl, Python, Skill, etc.

- Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decks

## Skills

### Required
- Cadence
- Virtuoso
- DRC
- LVS
- Dracula
- Hercules
- Calibre
- Perl
- Python
- Skill

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Taiwan-Taipei/Senior-Mask-Layout-Design-Engineer_JR2019959?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)