# Physical Design Engineer I (Co-op) - United States

**Company**: Cisco
**Location**: Maynard, Massachusetts
**Work arrangement**: onsite
**Experience**: entry
**Job type**: internship
**Salary**: $44,000.00 - $185,000.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Maynard-Massachusetts-US/Physical-Design-Engineer-I--Co-op----United-States_2026763?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_1cf9f61b-d9c

## Description

We're seeking a Physical Design Engineer I (Co-op) to join our Acacia PD team at Cisco. As a co-op student, you'll work on Cisco's elite optical communication products, contributing to the design, development, and optimization of physical floorplans and their implementation using the latest submicron technologies.

Your responsibilities will include:

- Collaborating with Front-End teams to ensure optimal physical implementation

- Performing gate-level netlist synthesis and physical implementation

- Optimizing power, performance, and area of design

- Conducting static timing analysis and signoff closure

- Ensuring physical verification and signoff closure

- Analyzing EMIR and achieving signoff closure

To qualify, you should:

- Be currently enrolled in an undergraduate degree program in Computer Science, Electrical Engineering, or a related field

- Have knowledge of the design cycle from RTL to GDSII

- Understand static timing analysis, timing closure, and design constraints

- Familiarize yourself with block-level synthesis, place and route, timing closure, PnR, and signoff tools

Preferred qualifications include:

- Interest in VLSI design, ASIC physical design, and verification

- Experience with deep submicron CMOS technologies

- Scripting skills in Perl, Tcl, Python, or shell

- Strong analytical and problem-solving skills

As a Cisco employee, you'll have access to various benefits, including medical, dental, and vision insurance, a 401(k) plan, paid parental leave, and more. Salary ranges vary by location, with specific ranges provided for certain areas.

## Skills

### Required
- RTL to GDSII design cycle
- Static Timing Analysis
- design constraints
- block-level synthesis
- place and route
- PnR
- signoff tools

### Nice to have
- VLSI design
- ASIC physical design
- verification
- deep submicron CMOS technologies
- Perl
- Tcl
- Python
- shell scripting

---

Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Maynard-Massachusetts-US/Physical-Design-Engineer-I--Co-op----United-States_2026763?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)