# ASIC Verification Engineering Intern

**Company**: Hewlett Packard Enterprise
**Location**: Roseville, CA
**Work arrangement**: hybrid
**Experience**: entry
**Job type**: internship
**Salary**: Hourly Salary USD 35.00 - 41.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Roseville-California-United-States-of-America/ASIC-Verification-Engineering-Intern_1214219?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_1b6515d5-dfc

## Description

Aruba, a Hewlett Packard Enterprise Company, is seeking an ASIC Post-Si Verification Engineering Intern to join our team in Roseville, CA.

The intern will work with the HPE Aruba ASIC development team on next-generation products, contributing to the development activities of current or future ASICs.

Responsibilities:

- Work with senior members of the ASIC/VLSI team on RTL/Physical Design, Pre-Silicon verification, Post-Silicon verification, Formal Verification, Script &/or Tool development, and other duties.

- Collaborate with the team to deliver state-of-the-art, world-class Networking Chips.

Education & Experience:

- Currently pursuing a Bachelor's or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related technical field.

- At least 3rd Year of engineering courses completed.

Knowledge & Skills:

- Basic programming or scripting knowledge (e.g., Verilog, SystemVerilog, Python, PERL, TCL, C, C++).

- Experience with hardware design.

- Strong interest in high-tech and a passion for learning.

- Excellent communication and interpersonal skills.

- Strong problem-solving and analytical skills.

- Ability to work within a team environment.

The expected salary/wage range for this position is: Hourly Salary USD 35.00 - 41.00 in California.

We offer a comprehensive suite of benefits that supports physical, financial, and emotional wellbeing, as well as opportunities for personal and professional development.

## Skills

### Required
- Verilog
- SystemVerilog
- Python
- PERL
- TCL
- C
- C++
- hardware design

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Source: [Apply at hpe.wd5.myworkdayjobs.com](https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Roseville-California-United-States-of-America/ASIC-Verification-Engineering-Intern_1214219?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)