# Senior Design Engineer

**Company**: NVIDIA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Design-Engineer---XBAR-IP_JR2027193?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_1b511a54-f0a

## Description

NVIDIA is seeking a Senior Design Engineer to join its Graphics team, working on the design of state-of-the-art memory subsystem components used in their industry-leading Graphics Processors.

In this position, you will make architectural trade-offs based on features, performance requirements, and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design.

**Responsibilities:**

- Own micro-architecture and RTL development of design modules.

- Micro-architect features to meet performance, power, and area requirements.

- Work with HW architects to define critical features.

- Collaborate with verification teams to verify the correctness of implemented features.

- Co-operate with timing, VLSI, and Physical design teams to ensure design meets timing, interface requirements, and is routable.

- Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested.

- Work on post-silicon verification and debug.

**Requirements:**

- BS/MS or equivalent experience.

- 4+ years of design experience.

- Experience in RTL design of complex design units for at least two or three projects.

- Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).

- Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.

- Expertise in Verilog.

**Nice to Have:**

- Design experience in memory subsystem or network interconnect IP.

- Good debugging and problem-solving skills.

- Scripting knowledge (Python/Perl/shell).

- Leadership experience in leading small 2-3 member teams.

- Good interpersonal skills and ability & desire to work as a part of a team.

## Skills

### Required
- RTL design
- ASIC design flow
- Verilog
- VCS
- Debussy
- GDB

### Nice to have
- memory subsystem
- network interconnect IP
- Python
- Perl
- shell scripting
- leadership experience

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Design-Engineer---XBAR-IP_JR2027193?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)