# SoC Engineer **Company**: OpenAI **Location**: San Francisco **Work arrangement**: hybrid **Experience**: senior **Job type**: Full time **Salary**: $287K - $485K **Category**: Engineering **Industry**: Technology **Wikidata**: https://www.wikidata.org/wiki/Q124605186 **Apply**: https://jobs.ashbyhq.com/openai/e8e7fd72-bc4e-4717-8a67-81e4798372c7?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_1991729d-f09 ## Description ## Compensation $287K – $485K • Offers Equity The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. ## Benefits - Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts - Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit) - 401(k) retirement plan with employer match - Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks) - Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees - 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law) - Mental health and wellness support - Employer-paid basic life and disability coverage - Annual learning and development stipend to fuel your professional growth - Daily meals in our offices, and meal delivery credits as eligible - Relocation support for eligible employees - Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided. ## About the Team OpenAI’s Hardware organization develops custom silicon and systems for advanced AI workloads. Our first-party accelerator team works across chip architecture, design, software, and systems to build the computing platforms that power frontier models. ## About the Role We’re looking for a SoC Engineer to help architect, design, and integrate OpenAI’s first-party AI accelerators. You will build the processor, interconnect, I/O, and platform infrastructure that connects our accelerator designs into complete, functional systems. ## Responsibilities - Define and implement SoC architectures spanning embedded processors, AMBA interconnects, peripheral subsystems, PCI Express, Ethernet and die-to-die interfaces. - Develop the microarchitecture and RTL design of subsystems supporting I/O and SoC functionality. - Integrate Arm Cortex-M and Cortex-A processors, AXI/APB fabrics, and third-party controller IP, including the RTL and glue logic needed to connect these components. - Develop reset and boot architectures, working with firmware and software teams to define sequencing, initialization, and survivability behavior. - Incorporate debug, test, and security requirements into the SoC architecture and implementation, partnering with other silicon designers to make the silicon observable, testable, and secure. - Drive PCIe and other I/O integration, including controller and PHY interfaces, high-speed SerDes, and die-to-die connectivity. - Contribute to power management and security architecture and design. - Work directly with third-party IP vendors to define technical requirements, evaluate IP capabilities, coordinate deliverables, and resolve issues from integration through silicon bring-up. - Work across architecture, design, verification, physical design, and software teams to define interfaces, resolve integration issues, and carry designs through pre-silicon validation and post-silicon bring-up. - Work closely with Firmware and Software teams to define boot, configuration and runtime behavior and functionality. - Build and apply automation and AI-assisted tools to accelerate design, IP integration, consistency checking, and debugging while maintaining engineering quality. ## Requirements - Experience in SoC architecture, RTL design, and subsystem or full-chip integration, with hands-on ownership through implementation and silicon bring-up. - Familiarity with Arm processor subsystems, including Cortex-M and Cortex-A, and AMBA protocols and interconnects such as AXI and APB. - Understanding of PCIe protocols and experience configuring, integrating, and debugging controller IP. - Experience integrating high-speed I/O, including SerDes/PHY interfaces and die-to-die links. - Experience working directly with third-party IP vendors to evaluate technical fit, communicate requirements, and drive integration and debug issues to resolution. - Understanding of reset and boot architecture and the interactions between hardware, firmware, and software during initialization and recovery. - Experience designing for debug, test, and security, and can reason about how these requirements affect the broader system. - Comfortable writing and debugging Verilog/SystemVerilog and building scripts or tools to make integration work more efficient and reliable. - Enjoy stretching into multiple domains, learning unfamiliar parts of a system, and rolling up your sleeves to build and debug. - Enjoy working on a small, dynamic team where priorities evolve and engineers take broad ownership. - Excited about creatively applying automation and AI tools to hardware design and integration work. ## Skills ### Required - SoC architecture - RTL design - subsystem or full-chip integration - Arm processor subsystems - AMBA protocols and interconnects - PCIe protocols - high-speed I/O - third-party IP vendors - reset and boot architecture - debug, test, and security - Verilog/SystemVerilog --- Source: [Apply at jobs.ashbyhq.com](https://jobs.ashbyhq.com/openai/e8e7fd72-bc4e-4717-8a67-81e4798372c7?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)