# Physical Design Engineer

**Company**: Cisco
**Location**: San Jose, California
**Experience**: senior
**Job type**: full-time
**Salary**: $186,900.00 - $267,700.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2014635?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_1944342e-d1e

## Description

The Common Hardware Group (CHG) at Cisco is looking for a Physical Design Engineer to create innovative hardware platforms central to the AI era. You will work on designing and implementing full-chip floorplans, collaborating with system and package design teams, and performing hierarchical implementation flows. You will also analyze existing tool flows and methodologies to identify efficiency gaps and implement enhancements.

Responsibilities:

- Perform full-chip floorplanning, taking into account architecture, foundry integration guidelines, and IP placement constraints

- Collaborate with system and package design teams to understand requirements and incorporate them into the full-chip floorplan

- Conduct hierarchical implementation flow, including partition, pin assignment, clock plan, and bump planning

- Implement RTL-to-GDSII flow, including floorplan, power grid plan, place and route, static timing analysis, power integrity, physical verification, and equivalence checks

- Analyze existing tool flows and methodologies to identify efficiency gaps and implement incremental or transformative enhancements

- Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology

- Utilize proficiency in low-power design methodologies using UPF

- Define signoff methodologies with foundry and standard cell IP vendors and validate/adjust them based on feedback from Post-Silicon Validation teams

- Leverage AI tools to improve productivity

Requirements:

- Bachelor's Degree in Electrical Engineering with 8+ years of Physical Design experience, Master's Degree with 6+ years, or PhD with 3+ years

- Experience working on full-chip activities

- Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies

- Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre/Pegasus

Preferred Qualifications:

- Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis

- Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions

- Experience in full-chip floor-planning and power grid planning

- Experience with custom clock (H-Tree or Mesh) at chip level

- Experience with Python and usage of AI tools

Benefits:

- Medical, dental, and vision insurance

- 401(k) plan with Cisco matching contribution

- Paid parental leave

- Short and long-term disability coverage

- Basic life insurance

- Paid time away (holidays, birthday, personal wellness days)

- Flexible vacation time off program

- Sick time off

- Additional paid time away for critical or emergency issues

- Optional 10 paid days per year to volunteer

Salary Range: $186,900.00 - $267,700.00

## Skills

### Required
- Physical Design
- RTL2GDSII flow
- EDA tools
- Low-power design methodologies

### Nice to have
- Hierarchical design
- Timing closure
- Power integrity analysis
- Python
- AI tools

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2014635?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)