# SerDes/DSP System, Architect

**Company**: Synopsys
**Location**: Sunnyvale
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Salary**: $209,000-$313,000
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/sunnyvale/serdes-dsp-system-architect-17009/44408/94499265904?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_174905b1-502

## Description

We are hiring a SerDes/DSP System Architect to join our team at Synopsys. As a key member of our R&D team, you will be responsible for developing and maintaining SerDes system models for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.

Your primary responsibilities will include running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels, designing and proposing advanced algorithms to calibrate and adapt transceivers for optimal performance, correlating simulated performance with silicon measurements to ensure accuracy and reliability, providing expert assistance to customers for system-level performance issues and troubleshooting, collaborating with cross-functional teams of analog, digital, and hardware engineers throughout all stages of development and post-silicon, and contributing to lab testing and analysis for high-speed serial links, ensuring robust design validation.

As a SerDes/DSP System Architect, you will have the opportunity to accelerate the development of bleeding-edge silicon IP, drive innovation in high-speed SerDes design, set industry benchmarks for performance and reliability, enhance product differentiation for customers, reduce risk and time-to-market for complex silicon products, expand the reach of Synopsys' portfolio, and empower customers with technical expertise and hands-on support.

To be successful in this role, you will need to have a strong background in analog, digital, and communications theory, with a focus on high-speed serial-link transceiver development. You should have a solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk filtering, and experience with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).

You will also need to have hands-on lab testing experience for high-speed serial links and proficiency in C/Verilog-A/system Verilog. Programming in Python is a plus.

If you are a motivated and innovative thinker with a passion for cutting-edge technology, a collaborative team player who thrives in a multidisciplinary environment, an analytical problem-solver with meticulous attention to detail, and an effective communicator who can translate complex concepts for diverse audiences, then we encourage you to apply for this exciting opportunity.

## Skills

### Required
- MATLAB/Simulink
- DSP and communications theory
- equalization
- encoding
- noise/crosstalk filtering
- wireline protocols (PCIe, Ethernet, JESD204C, CPRI)
- optical protocols (LINEAR, RTLR)
- C/Verilog-A/system Verilog
- Python

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/sunnyvale/serdes-dsp-system-architect-17009/44408/94499265904?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)