# ASIC Timing Engineer

**Company**: NVIDIA
**Experience**: senior
**Job type**: full-time
**Salary**: $136,000 - $218,500 (Level 3), $168,000 - $264,500 (Level 4)
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Timing-Engineer_JR2026198-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_17229e04-be2

## Description

NVIDIA is seeking a motivated ASIC Timing Engineer to join its dynamic team.

The successful candidate will drive timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at various levels.

Key responsibilities:

- Lead timing analysis and closure for block, cluster, and full-chip levels

- Collaborate with cross-functional teams to devise timing closure strategies and drive timing and power convergence

- Contribute to cutting-edge projects and improve timing convergence flows

Requirements:

- BS/MS in Electrical or Computer Engineering with 5/3 years of experience in Timing and STA

- Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence

- Expertise in analysis and fixing of timing paths through ECOs

- Experience in physical design and optimization

- Knowledge of industry-standard STA and timing convergence tools

- Understanding of deep sub-micron process nodes

Preferred qualifications:

- Background in domain-specific STA and timing convergence for GPUs, CPUs, LPU, or SOCs

- Experience in logic synthesis and equivalence checking/FV

- Understanding of DFT logic and experience with DFT timing closure

- Knowledge of digital logic/macros in AMS designs/IPs

- Experience in methodology and/or flow development and automation

NVIDIA offers a competitive salary ranging from $136,000 to $264,500, depending on experience and location, as well as equity and benefits.

## Skills

### Required
- STA
- timing convergence
- physical design
- ECOs
- DFT

### Nice to have
- domain-specific STA
- logic synthesis
- equivalence checking
- DFT timing closure
- AMS designs

---

Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Timing-Engineer_JR2026198-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)