# SOC Clocks RTL Design Engineer

**Company**: NVIDIA
**Location**: Tel Aviv, Israel
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Tel-Aviv/SOC-Clocks-RTL-Design-Engineer_JR2022321?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_165db122-7df

## Description

The NVIDIA System-On-Chip (SOC) group is looking for a strong RTL Design Engineer to own the SOC clocking logic for our next-generation networking chips.

In this role, you will own the clock generation, distribution, and control logic for the entire chip , PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.

**Responsibilities:**

- Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out

- Defining and implementing the SOC clock and reset architecture together with the micro-architecture team , collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design

- Owning clock domain crossing infrastructure and CDC closure across the SOC

- Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power

- Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness

- Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows

- Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks

- Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable

- Supporting emulation, firmware, and post-silicon bring-up customers of your design

**Requirements:**

- B.Sc./M.Sc. in Electrical Engineering or Computer Engineering

- 3+ years of relevant experience in RTL/logic design

- Solid hands-on RTL design skills in Verilog/SystemVerilog, with a good understanding of synthesis, timing, and how RTL choices affect the physical implementation

- Experience taking a design from micro-architecture specification through verification and physical implementation

- Solid understanding of clocking and reset concepts: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing

- Familiarity with design quality tooling (lint, CDC/RDC, formal, synthesis)

- Great teammate with strong communication skills across micro-architecture, DV, and backend teams

## Skills

### Required
- RTL design
- Verilog
- SystemVerilog
- clocking and reset concepts
- design quality tooling

### Nice to have
- PLL/clock generator integration
- clock tree constraint development

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Tel-Aviv/SOC-Clocks-RTL-Design-Engineer_JR2022321?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)