# ASIC Design Verification Engineer

**Company**: Cisco
**Location**: San Jose, California
**Experience**: senior
**Job type**: full-time
**Salary**: $167,700.00 - $245,200.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Sr-ASIC-Design-Verification-Engineer_2008446?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_15007d5e-c52

## Description

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks.

Your Impact:

- Participate in ASIC design verification for Cisco high-end switching products.

- Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure.

- Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis.

- Construct testbenches components like scoreboard, agents, sequencers, and monitors.

- Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration.

- Ensure comprehensive verification coverage through code and functional coverage implementation and review.

Minimum Qualifications:

- Bachelor's degree in electrical/computer science/computer engineering/related degree and 7+ years of related experience or Master's in electrical/computer science/computer engineering/related degree and 4+ years of related experience, or PhD in electrical/computer science/computer engineering/related degree + 1 year of related experience.

- Prior experience in System Verilog and UVM.

- Experience with ASIC design and verification processes, debugging, methodology, and tools.

- Experience in verifying blocks/clusters or full chip level for ASIC.

Preferred Qualifications:

- Hands-on experience with Ethernet protocols and high-speed SerDes interfaces.

- Proficiency in Linux and programming languages such as C/C++ and/or Python/Perl.

- Strong understanding of networking fundamentals and system-level architectures.

- Working knowledge of PCIe and AXI protocols.

- Experience with post-silicon bring-up and lab debugging.

- Experience in data center, hyperscalers, or AI networking environments.

- Proven contributions to industry standards or ASIC verification best practices.

- Deep expertise in multiple protocols and large-scale SoC architectures.

Benefits:

- Medical, dental, and vision insurance.

- 401(k) plan with Cisco matching contribution.

- Paid parental leave.

- Short and long-term disability coverage.

- Basic life insurance.

- Paid time away (vacation, holidays, sick time).

- Optional 10 paid days per full calendar year to volunteer.

Salary Range: $167,700.00 - $245,200.00

## Skills

### Required
- System Verilog
- UVM
- ASIC design
- verification

### Nice to have
- Ethernet protocols
- SerDes interfaces
- Linux
- C/C++
- Python/Perl
- PCIe
- AXI protocols

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Sr-ASIC-Design-Verification-Engineer_2008446?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)