# Senior Design Verification Engineer

**Company**: Hewlett Packard Enterprise
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: Annual Salary USD 153,500 - 310,500
**Category**: Engineering
**Industry**: Technology

**Apply**: https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Sunnyvale-California-United-States-of-America/Senior-Design-Verification-Engineer_1208455-2?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_12da8557-57f

## Description

We are seeking a talented and driven Senior Design Verification Engineer with specialized knowledge and experience in emulation-based verification to join our engineering team.

In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs, ensuring functional correctness and performance targets are met prior to silicon tape-out.

Key responsibilities:

- Develop and execute verification plans for IP-level and system-level designs

- Build, maintain, and enhance UVM/SystemVerilog-based testbench environments

- Develop and run directed and constrained-random test cases to achieve functional and code coverage goals

- Set up, configure, and run designs on emulation platforms for system-level verification and performance validation

- Collaborate with design teams to define verification strategies and review specifications

- Debug complex design issues using waveform analysis and emulation platform debug tools

- Drive coverage closure and generate verification sign-off reports

Requirements:

- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

- 5-8 years of professional experience in design verification of digital/mixed-signal designs

- Strong proficiency in SystemVerilog and UVM methodology

- Hands-on experience with emulation-based verification platforms

- Solid understanding of digital design concepts, including RTL design, synthesis constraints, and timing

Preferred qualifications:

- Master's degree in Electrical Engineering, Computer Engineering, or a related field

- Experience with networking protocols such as Ethernet, TCP/IP, PCIe, or CXL

- Knowledge of communication and interface protocols, including AXI, AHB, APB, AMBA, I2C, SPI, or UART

- Experience with formal verification tools and techniques

- Familiarity with FPGA prototyping platforms and flows

We offer a comprehensive suite of benefits that supports physical, financial, and emotional wellbeing, as well as opportunities for personal and professional development.

## Skills

### Required
- SystemVerilog
- UVM
- emulation-based verification
- digital design
- verification strategies

### Nice to have
- networking protocols
- communication and interface protocols
- formal verification
- FPGA prototyping

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