# ASIC Design Verification Engineer

**Company**: Cisco
**Location**: Bangalore
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Bangalore-India/ASIC-Verification-Technical-Leader_2023398?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_10f02a30-2dd

## Description

The Common Hardware Group (CHG) at Cisco designs and develops silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products.

You will contribute to developing Cisco's progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security.

Responsibilities:

- Architect block, cluster, and top-level DV environment infrastructure.

- Develop DV infrastructure from scratch.

- Maintain and improve existing DV environments.

- Develop test plans and tests for qualifying design at block, cluster, and higher-level environments with a mix of constraint random and advised stimulus.

- Ensure complete verification coverage through implementation and review of code and functional coverage.

- Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist.

- Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance.

- Support testing of design in emulation.

- Lead all aspects of and manage the ASIC bring-up process.

Minimum Qualifications:

- Bachelor's degree or master's degree in EE, CE, or other related field.

- 10+ years of related ASIC design verification experience.

- Proficient in ASIC verification using UVM/System Verilog.

- Proficient in verifying sophisticated blocks, clusters, and top-level ASICs.

- Experience building test benches from scratch, hands-on experience with System Verilog constraints, structures, and classes.

- Scripting experience with Perl and/or Python.

Preferred Qualifications:

- Experience with Networking ASICs.

- Experience with Forwarding logic/Parsers/Buffer management/Arbitration and scheduling.

- Experience with Veloce/Palladium/Zebu/HAPS.

- Formal verification (iev/vc formal) knowledge.

- Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, IPv4/6, TCP).

Benefits: No specific benefits mentioned.

## Skills

### Required
- ASIC design verification
- UVM/System Verilog
- Perl
- Python

### Nice to have
- Networking ASICs
- Forwarding logic
- Veloce/Palladium/Zebu/HAPS
- Formal verification

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Bangalore-India/ASIC-Verification-Technical-Leader_2023398?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)